PARALLEL BUS REVEALED Conclusion of the first-ever PBI usage guide

Posted on Feb 5, 2014

This article includes an assembly language listing that requires MAC/65 or Atari Assembler Editor. You will also need access to an EPROM burner. The three earlier installments ran in the January, February and March 1985 issues of Antic. This USART design is a simplest case design. Writing to any address in the $D100-$D1FF range puts a character i

PARALLEL BUS REVEALED Conclusion of the first-ever PBI usage guide

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nto the transmit buffer and it will be sent out the serial I/O line. Reading any address in the same range gets the last received character from the receive buffer. The easiest way to test this arrangement is to tie the serial input and output lines (USART pins 20 and 25) together. If you write a character to the transmit buffer and wait a few milliseconds, you should be able to read the same character from the receive buffer. All this assumes that we`re decoding addresses and that we have some software in ROM, so let`s get on with those details. The output signal $D8XX-$DFXX, combined with the Device Select signal (DEVSEL), provides the Math Pack Disable signal (MPD) to disable the floating point ROM in the CPU so it doesn`t contend with our ROM for the data bus. We can use the same signal to select our ROM. This allows us to remove some of the logic from last month`s circuit. Just remove the wires from 1C4 pins 6, 5, 4, 13, 12 and 11 and connect MPD to ROM pin 20. (See last month`s Figure 2). The signal $DlFF selects the Device Enable Latch. When a write signal clocks the 74HCT74 latch, the value of the Data 0 line (D0) will be stored. Writing 1 to address $DlFF selects our external device. Writing 0 deselects it. $DlFF can also be used later to select an interrupt register. By combining it with DEVSEL and $DlXX, we get a Device Register Enable signal (DRE). We`ll use this signal instead of part of the logic in last...

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