interfacing spi adc with spartan 6 fpga


Posted on Feb 5, 2014

The Spartan-6 board has 2-channel 12 Bit SPI ADC, indicated as in Figure. As you know in synchronous serial communication there is a clock line (SCK in case of SPI) which synchronizes the transfer. The clock is always controlled by the MASTER. In our case the Spartan6 is the MASTER and the MCP3202 is a slave on the bus. SPI is full duplex, which m


interfacing spi adc with spartan 6 fpga
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eans data can be sent and received simultaneously. A SPI transfer is initiated by the MASTER pulling the CS line low. The CS line sits at HIGH during idle state. Now master can write to the bus in 8bit (or 1 byte) chunks. One most important thing to note about SPI is that for every byte MASTER writes to SLAVE the MASTER receives one byte in return. So the only transaction possible is exchange of data.




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