74123

74123 Dual Retriggerable Monostable Multivibrator Technical Summary

Overview

The 74123 is a dual retriggerable monostable multivibrator integrated circuit belonging to the M54/M74HC123 family. This component provides precision timing capabilities through external resistor and capacitor networks, making it highly versatile for pulse generation applications. Each IC contains two independent multivibrators with clear functionality, allowing for flexible timing control in digital systems.

Key operational aspects include:

• Retriggerable design enables pulse width extension during active output
• Direct clear input for immediate termination of output pulse
• Internal parasitic diode for capacitor discharge protection
• Wide operating voltage range compatible with TTL and CMOS systems

Features

• Dual Monostable Circuits: Two independent multivibrators in one package
• Retriggerable Operation: Pulse width can be extended by subsequent triggers
• Clear Function: Immediate output termination via clear input
• Wide Timing Range: From nanoseconds to seconds depending on external components
• Low Power Consumption: Typical standby current of 20μA
• High Noise Immunity: Typical noise margin of 1V at VCC = 5V
• Output Drive Capability: 10 LSTTL loads
• Operating Voltage Range: 2V to 6V (HC series)

Applications

The 74123 finds use in numerous timing and pulse generation applications including:

• Precision timing circuits
• Pulse width modulation systems
• Debounce circuits for mechanical switches
• Frequency dividers
• Time delay generation
• Missing pulse detectors
• Waveform generators
• Power-up reset circuits

Electrical Characteristics

Key electrical parameters at VCC = 5V and TA = 25°C:

DC Characteristics

• High Level Input Voltage: 3.15V min
• Low Level Input Voltage: 1.35V max
• High Level Output Voltage: 4.4V min (IOH = -4mA)
• Low Level Output Voltage: 0.33V max (IOL = 4mA)
• Input Leakage Current: ±1μA max
• Quiescent Supply Current: 20μA max

AC Characteristics

• Propagation Delay (A/B to Q): 15ns typical
• Propagation Delay (A/B to Q̅): 20ns typical
• Output Transition Time: 6ns typical
• Maximum Clock Frequency: 50MHz typical

Timing Characteristics

The output pulse width is determined by the external timing components:

• For Cx > 1000pF: tw ≈ 0.28 × Rx × Cx × (1 + 0.7/Rx)
• For Cx ≤ 1000pF: See manufacturer's nomographs
• Minimum Rx: 5kΩ
• Minimum Cx: None (parasitic capacitance ≈ 10pF)

Package Information

The 74123 is available in multiple package options:

Standard Package Options

• DIP-16: 0.3" wide plastic dual in-line package
• SOIC-16: 150 mil body width surface mount package
• TSSOP-16: Thin shrink small outline package

Pin Configuration (DIP-16)

• Pin 1: 1A (Trigger Input for first multivibrator)
• Pin 2: 1B (Trigger Input for first multivibrator)
• Pin 3: 1CLR (Clear Input for first multivibrator)
• Pin 4: 1Q (Output for first multivibrator)
• Pin 5: 1Q̅ (Complementary Output for first multivibrator)
• Pin 6: 1Cx (External Capacitor Connection)
• Pin 7: 1Rx/Cx (External Resistor/Capacitor Connection)
• Pin 8: GND (Ground)
• Pin 9: 2Rx/Cx (External Resistor/Capacitor Connection)
• Pin 10: 2Cx (External Capacitor Connection)
• Pin 11: 2Q̅ (Complementary Output for second multivibrator)
• Pin 12: 2Q (Output for second multivibrator)
• Pin 13: 2CLR (Clear Input for second multivibrator)
• Pin 14: 2B (Trigger Input for second multivibrator)
• Pin 15: 2A (Trigger Input for second multivibrator)
• Pin 16: VCC (Positive Supply Voltage)

Functional Description

The 74123 operates as a precision monostable multivibrator with the following states:

Standby State

In standby (no trigger applied), the external capacitor Cx charges to VCC through the internal circuitry. The output remains in its stable state (Q low, Q̅ high). The device consumes minimal power in this state.

Triggering

A trigger event occurs when either the A or B inputs meet the specified transition requirements. The trigger can be initiated by either:

• A high-to-low transition on A with B high
• A low-to-high transition on B with A low

Timing Period

During the timing period, the output changes state (Q goes high, Q̅ goes low) for a duration determined by the external Rx and Cx components. The device can be retriggered during this period to extend the output pulse.

Clear Function

Applying a low pulse to the CLR input immediately terminates the output pulse, regardless of the timing period completion. This provides direct control over the output state.

Design Considerations

Important design factors when using the 74123:

Capacitor Discharge Protection

The internal parasitic diode (maximum forward current 20mA) provides discharge protection for the external capacitor when power is removed. For large capacitors, the supply voltage fall time must meet:

tf ≥ (VCC - 0.7) × Cx / 20mA

If this condition cannot be met, an external clamping diode is required to protect the IC from surge currents.

Noise Immunity

For reliable operation in noisy environments:

• Keep timing components close to the IC
• Use bypass capacitors (0.1μF) near VCC
• Minimize lead lengths on high impedance nodes

Power Supply Considerations

The device operates across a wide voltage range (2V to 6V for HC series). Power supply sequencing is not critical, but rapid power-down with large timing capacitors should be avoided.