Hardware histogram speeds ADC test


Posted on Nov 21, 2012

The circuit of Figure 1 shows how you can configure a FIFO memory, a static SRAM, and a bus register to generate fast hardware histograms for linearity tests and still allow straight data acquisition for other tests. The main purpose of the FIFO memory is to collect data at the speed of the DUT (device under test), because, with all the data-swapping that occurs during the histogram routine, the cycle is slower than the DUT.






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