gcr
A 5-pole elliptic low pass filter (impedance: 50 Ohm, -6 dB cutoff frequency 33 MHz) connects the antenna signal to the diode ring mixer, a traditional SBL-1, which performs well even below 500 kHz. A high pass/low pass diplexing filter directs the 45 MHz mixing products to a first IF amplifier, while the lower frequency mixing products are wasted in a 50 Ohm load. The necessity of the diplexing filter is uncertain, as the first IF amplifier already provides a fairly broad bandwidth and low input impedance, but it is believed that it does not significantly detract from performance. The first IF amplifier is based on the well-known Hayward & Lawson design, utilizing a BF494 transistor with a moderate transition frequency of 250 MHz. The collector current is set to a relatively high 15 mA, enhancing the dynamic range. The output transformer increases the relatively low load impedance by a factor of 9, boosting collector load and consequently gain. A 6 dB attenuator establishes the output impedance of the first IF amplifier at 2500 Ohm, which matches the impedance of the 45 MHz IF filter. The total gain was measured at 15 dB, including the attenuator. The 45 MHz IF filter consists of a paired set of two-pole monolithic crystal filters, sold by Golledge as GMCF-45-45G15B1. It provides a bandwidth of 15 kHz (3 dB ripple), a stopband rejection of 70 dB, and an impedance of 650 Ohm, according to Golledge's website. A second IF amplifier mirrors the first, but with a higher input impedance, completing the receiver front end. The overall gain for the entire front end combination of filters, mixers, and amplifiers was measured at 13 dB. When cascaded with the ELEKTOR DRM-RX module, a total gain (HF to 12 kHz) of 36 dB is achieved, sufficient for a minimum detectable signal (MDS) of less than 1 µV. A single voltage-controlled VHF oscillator, tunable between 45 and 75 MHz, presents significant challenges. Compromises must be made between range and oscillation conditions to achieve the desired output level (flat across the tuning range) and low noise. Initial attempts with a Colpitts oscillator using a switchable inductor failed to oscillate. Ultimately, two minimalist Hartley oscillators, each handling half the range, were adopted. The use of a J310 J-FET ensures low noise operation, while minimal coupling with a buffer amplifier (based on a BF245C J-FET) ensures stability. For tuning, a lightly coupled KV1260, a dual variable capacitance diode used in AM radios, is employed. Connecting both diodes in series enhances circuit linearity. VCO stabilization is achieved using a phase-locked loop (PLL) based on the MC145170. The VCO signal is buffered again (by a BF494), with an additional 6 dB gain required to meet the input level limits of the PLL chip. The reference signal of approximately 440 kHz is sourced from the DDS on the original ELEKTOR DRM-RX module (at the collector of T1). This signal is routed through a pair of coupled resonators (de-tuned 455 kHz IF transformers) to clean the signal slightly and is subsequently amplified (by another BF494) before being fed into the PLL chip's reference input. This 440 kHz signal is then further divided by 44 (using the reference divider in the chip), producing a 10 kHz reference for the phase/frequency comparator. This relatively high frequency was selected to further reduce the noise skirts of the VCO, as more of it falls within the bandwidth of the loop. Sub-10 kHz frequency settings are achieved by slightly offsetting the 10 kHz reference. For example, a local oscillator frequency of 55,000,000 Hz (for a 10 MHz reception) would be realized with a main divider setting of 5500, a reference divider setting of 44, and by injecting a reference of 440,000,000 Hz from the DDS, with the increment being 37,795,712 for a 50 MHz clock. For a frequency of 55,000,010 Hz (10 Hz more), the PLL settings would remain consistent.
The described circuit architecture effectively integrates a series of filters and amplifiers to achieve a robust radio frequency (RF) front end. The 5-pole elliptic low pass filter ensures that unwanted high-frequency signals are attenuated before reaching the mixer, while the SBL-1 diode ring mixer efficiently combines the RF signal with the local oscillator signal, generating intermediate frequency (IF) signals suitable for further amplification and processing. The first IF amplifier is designed to enhance the signal strength while maintaining a low noise figure, crucial for receiving weak signals. The choice of components, such as the BF494 transistor, is critical in achieving the desired performance metrics, including dynamic range and gain.
The diplexing filter, although debated in necessity, serves to separate the 45 MHz mixing products from lower frequency signals, ensuring that the first IF amplifier operates within its optimal range. The use of monolithic crystal filters for the 45 MHz IF stage further refines the signal, providing excellent selectivity and rejection of unwanted frequencies. The second IF amplifier's design mirrors the first but is tailored to accommodate a higher input impedance, enhancing the overall receiver performance.
The VCO design, incorporating Hartley oscillators and J-FETs, exemplifies a balance between operational range and noise performance. The stabilization provided by the PLL ensures that the VCO maintains a stable output frequency, essential for coherent demodulation of the received signals. The careful selection of reference frequencies and dividers facilitates precise tuning, allowing for effective reception across the desired frequency range. Overall, this circuit exemplifies a well-engineered solution for RF signal processing, achieving high gain and low noise performance suitable for modern communication applications.An 5 pole elliptic low pass filter (impedance: 50Ohm, -6dB cut off frequency 33MHz) connects the antenna signal to the diode ring mixer, a traditional SBL-1, which offers good performance even below 500kHz. A high pass / low pass diplexing filter leads the 45MHz mixing products to a first IF amplifier, while the lower frequency mixing products are
wasted in a 50Ohm load. I am not too sure the diplexing filter is really needed as the first IF amplifier offers already a fairly broad band and low input impedance, but I don`t think it will hurt a lot. The first IF amplifier is derived from the well known Hayward & Lawson design, it uses a BF494 transistor featuring a moderate ft of 250MHz.
The collector current is set to a fairly high 15mA, improving the dynamic range. The output transformer converts the relatively low load impedance by a factor of 9, increasing collector load and hence the gain. A 6dB attenuator sets the output impedance of the first IF amplifier at 2500Ohm, which is the impedance of the 45MHz IF filter.
The total gain was measured at 15dB, including the attenuator. The 45MHz IF filter is a paired set of two pole monolithic crystal filters, sold by Golledge as GMCF-45 - 45G15B1 . It offers a bandwidth of 15kHz (3dB ripple), a stop band rejection of 70dB, and an impedance of 650Ohm, see Golledge`s Web site.
A second IF amplifier is similar to the first, having a higher input impedance though, and closes the receiver front end part. The overall gain was measured to be 13dB for the entire front end combination of filters, mixers and amplifiers.
Cascaded with the ELEKTOR DRM-RX module, a total gain (HF to 12kHz) of 36dB is achieved, which is adequate for an MDS of less than 1 µV. A single voltage controlled VHF oscillator tuneable between of 45 75MHz, a range almost 2, presents quite a challenge as I found out.
Compromises have to be made between the range and the very oscillation conditions, in order to achieve the required characteristics of output level (flat over the tuning range) and above all low noise (the least possible). An attempt was made with a Colpitts oscillator with a switchable inductor, it didn`t even oscillate !
Finally, I settled for two minimalist Hartley oscillators coping each with halve the range (see table). Using the J310 J-FET guarantees a good low noise operation; while a minimal coupling with the buffer amplifier (based on a BF245C J-FET) guarantees a good stability.
For the tuning a lightly coupled KV1260 is used, it is a dual variable capacitance diode used in AM radios. Using both diodes in series improves the linearity of the circuit even further. Stabilising the VCO is realised by a PLL based on the old faithful MC145170. The VCO signal is buffered once more (by a BF494), an extra 6dB being needed to get within the level limits of the PLL chip.
As mentioned earlier, the reference signal of approximately 440kHz is taken from the DDS on the original ELEKTOR DRM-RX module (at the collector of T1). This signal is led to a pair of coupled resonators (de-tuned 455kHz IF transformers), to clean the signal a bit and is subsequently amplified (by another BF494) before being fed to the PLL chip`s reference input.
This 440kHz is then further divided by 44 (by the reference divider in the chip), yielding the 10kHz reference for the phase/frequency comparator. This relatively high frequency was chosen in order to reduce the noise skirts of the VCO even more, as more of it is within the bandwidth of the loop.
Sub 10kHz frequency setting is realised by offsetting the 10kHz reference by a tiny amount. A LO frequency of e. g. 55, 000, 000Hz (for a 10MHz reception) would be realised with a main divider setting of 5500, a reference divider setting of 44 and by injecting a reference of 440, 000. 000Hz from the DDS, the increment being 37795712 for a 50MHz clock. For a frequency of 55, 000, 010Hz (10Hz more), the PLL settings would be the sa 🔗 External reference
The described circuit architecture effectively integrates a series of filters and amplifiers to achieve a robust radio frequency (RF) front end. The 5-pole elliptic low pass filter ensures that unwanted high-frequency signals are attenuated before reaching the mixer, while the SBL-1 diode ring mixer efficiently combines the RF signal with the local oscillator signal, generating intermediate frequency (IF) signals suitable for further amplification and processing. The first IF amplifier is designed to enhance the signal strength while maintaining a low noise figure, crucial for receiving weak signals. The choice of components, such as the BF494 transistor, is critical in achieving the desired performance metrics, including dynamic range and gain.
The diplexing filter, although debated in necessity, serves to separate the 45 MHz mixing products from lower frequency signals, ensuring that the first IF amplifier operates within its optimal range. The use of monolithic crystal filters for the 45 MHz IF stage further refines the signal, providing excellent selectivity and rejection of unwanted frequencies. The second IF amplifier's design mirrors the first but is tailored to accommodate a higher input impedance, enhancing the overall receiver performance.
The VCO design, incorporating Hartley oscillators and J-FETs, exemplifies a balance between operational range and noise performance. The stabilization provided by the PLL ensures that the VCO maintains a stable output frequency, essential for coherent demodulation of the received signals. The careful selection of reference frequencies and dividers facilitates precise tuning, allowing for effective reception across the desired frequency range. Overall, this circuit exemplifies a well-engineered solution for RF signal processing, achieving high gain and low noise performance suitable for modern communication applications.An 5 pole elliptic low pass filter (impedance: 50Ohm, -6dB cut off frequency 33MHz) connects the antenna signal to the diode ring mixer, a traditional SBL-1, which offers good performance even below 500kHz. A high pass / low pass diplexing filter leads the 45MHz mixing products to a first IF amplifier, while the lower frequency mixing products are
wasted in a 50Ohm load. I am not too sure the diplexing filter is really needed as the first IF amplifier offers already a fairly broad band and low input impedance, but I don`t think it will hurt a lot. The first IF amplifier is derived from the well known Hayward & Lawson design, it uses a BF494 transistor featuring a moderate ft of 250MHz.
The collector current is set to a fairly high 15mA, improving the dynamic range. The output transformer converts the relatively low load impedance by a factor of 9, increasing collector load and hence the gain. A 6dB attenuator sets the output impedance of the first IF amplifier at 2500Ohm, which is the impedance of the 45MHz IF filter.
The total gain was measured at 15dB, including the attenuator. The 45MHz IF filter is a paired set of two pole monolithic crystal filters, sold by Golledge as GMCF-45 - 45G15B1 . It offers a bandwidth of 15kHz (3dB ripple), a stop band rejection of 70dB, and an impedance of 650Ohm, see Golledge`s Web site.
A second IF amplifier is similar to the first, having a higher input impedance though, and closes the receiver front end part. The overall gain was measured to be 13dB for the entire front end combination of filters, mixers and amplifiers.
Cascaded with the ELEKTOR DRM-RX module, a total gain (HF to 12kHz) of 36dB is achieved, which is adequate for an MDS of less than 1 µV. A single voltage controlled VHF oscillator tuneable between of 45 75MHz, a range almost 2, presents quite a challenge as I found out.
Compromises have to be made between the range and the very oscillation conditions, in order to achieve the required characteristics of output level (flat over the tuning range) and above all low noise (the least possible). An attempt was made with a Colpitts oscillator with a switchable inductor, it didn`t even oscillate !
Finally, I settled for two minimalist Hartley oscillators coping each with halve the range (see table). Using the J310 J-FET guarantees a good low noise operation; while a minimal coupling with the buffer amplifier (based on a BF245C J-FET) guarantees a good stability.
For the tuning a lightly coupled KV1260 is used, it is a dual variable capacitance diode used in AM radios. Using both diodes in series improves the linearity of the circuit even further. Stabilising the VCO is realised by a PLL based on the old faithful MC145170. The VCO signal is buffered once more (by a BF494), an extra 6dB being needed to get within the level limits of the PLL chip.
As mentioned earlier, the reference signal of approximately 440kHz is taken from the DDS on the original ELEKTOR DRM-RX module (at the collector of T1). This signal is led to a pair of coupled resonators (de-tuned 455kHz IF transformers), to clean the signal a bit and is subsequently amplified (by another BF494) before being fed to the PLL chip`s reference input.
This 440kHz is then further divided by 44 (by the reference divider in the chip), yielding the 10kHz reference for the phase/frequency comparator. This relatively high frequency was chosen in order to reduce the noise skirts of the VCO even more, as more of it is within the bandwidth of the loop.
Sub 10kHz frequency setting is realised by offsetting the 10kHz reference by a tiny amount. A LO frequency of e. g. 55, 000, 000Hz (for a 10MHz reception) would be realised with a main divider setting of 5500, a reference divider setting of 44 and by injecting a reference of 440, 000. 000Hz from the DDS, the increment being 37795712 for a 50MHz clock. For a frequency of 55, 000, 010Hz (10Hz more), the PLL settings would be the sa 🔗 External reference