Measuring Voltage with ADS1115

1. Overview of the ADS1115 ADC

Overview of the ADS1115 ADC

The ADS1115 is a precision, low-power, 16-bit analog-to-digital converter (ADC) with an integrated programmable gain amplifier (PGA) and internal voltage reference. Its delta-sigma architecture provides excellent noise immunity while maintaining high resolution across a wide input voltage range (±6.144V maximum). The device communicates via I²C and offers four single-ended or two differential input channels with a programmable data rate from 8SPS to 860SPS.

Key Specifications and Performance Characteristics

The converter's resolution and accuracy are primarily governed by its effective number of bits (ENOB) and integral nonlinearity (INL). For the ADS1115:

The input stage's common-mode rejection ratio (CMRR) exceeds 90dB at 50Hz, making it suitable for noisy environments. The programmable gain amplifier offers selectable gains of 2/3×, 1×, 2×, 4×, 8×, 16×, allowing optimization for different signal ranges.

Conversion Process and Timing

The ADC employs a switched-capacitor delta-sigma modulator followed by a digital decimation filter. The conversion time (tCONV) depends on the selected data rate:

$$ t_{CONV} = \frac{1}{DR} + 0.2ms \quad \text{(where DR is data rate in SPS)} $$

For continuous conversion mode, the device automatically begins a new conversion immediately after completing the previous one. In single-shot mode, the converter enters a low-power state (0.5μA typical) between conversions.

Input Circuitry and Protection

The analog inputs feature ESD protection diodes rated for 2kV HBM and incorporate a switched-capacitor sampling network with 10pF nominal capacitance. The input impedance appears as:

$$ Z_{IN} = \frac{1}{2πf_{sample}C_{sample}} + R_{switch} $$

where Rswitch is typically 500Ω. External RC filters (1kΩ, 0.1μF recommended) help mitigate aliasing and provide additional protection.

Digital Interface and Configuration

The I²C interface supports standard (100kHz), fast (400kHz), and high-speed (3.4MHz) modes. Configuration registers control:

The 16-bit conversion results are stored in a two's complement format, with positive full-scale represented as 0x7FFF and negative full-scale as 0x8000.

Error Sources and Compensation

Major error contributors include:

$$ E_{total} = \sqrt{E_{offset}^2 + E_{gain}^2 + E_{noise}^2 + E_{INL}^2} $$

where Eoffset can be up to 125μV (calibratable), Egain ≤ 0.15% FSR, and Enoise depends on the selected data rate and gain. The device's internal temperature coefficient is typically 0.5μV/°C for offset and 5ppm/°C for gain.

ADS1115 Functional Block Diagram Block diagram showing the internal architecture of ADS1115 including input multiplexer, PGA, delta-sigma modulator, decimation filter, and I²C interface. Input Multiplexer AIN0 AIN1 AIN2 AIN3 PGA Gain: x1-x8 Delta-Sigma Modulator Digital Filter I²C Interface Config Registers Modulator Clock
Diagram Description: A block diagram would visually show the ADS1115's internal architecture including the PGA, delta-sigma modulator, and digital filter stages.

1.2 Key Features and Specifications

Resolution and Input Range

The ADS1115 is a 16-bit delta-sigma analog-to-digital converter (ADC), providing a resolution of 1 LSB = $$\frac{V_{FSR}}{2^{16} - 1}$$, where VFSR is the full-scale input voltage range. The programmable gain amplifier (PGA) allows adjustable input ranges:

The effective voltage resolution at ±6.144V is $$\frac{6.144 \times 2}{65535} \approx 187.5 \mu V$$ per LSB.

Sampling Rate and Noise Performance

The device supports data rates from 8 SPS to 860 SPS, configurable via the DR[2:0] bits in the config register. The signal-to-noise ratio (SNR) is given by:

$$ \text{SNR (dB)} = 6.02 \times N + 1.76 + 10 \log_{10}\left(\frac{f_s}{2 \times f_{BW}}\right) $$

where N is the ADC resolution (16 bits), fs is the sampling rate, and fBW is the input signal bandwidth. For 860 SPS, the typical noise floor is 0.256 mVRMS (±6.144V range).

Input Multiplexer and Differential Measurements

The integrated multiplexer supports four single-ended or two differential inputs. The common-mode rejection ratio (CMRR) exceeds 90 dB at 50 Hz, critical for rejecting ground loops in industrial environments. The differential input impedance is 6 MΩ (typ) in parallel with 10 pF.

Internal Reference and Offset Calibration

A 2.048V internal reference provides ±0.05% initial accuracy with 10 ppm/°C drift. The offset drift is ±0.3 μV/°C, enabling high-precision DC measurements without external calibration. The integral nonlinearity (INL) is ±2 LSB (max) across all gains.

I²C Interface and Power Efficiency

The 400-kHz I²C interface includes programmable address pins (0x48–0x4B). Power consumption scales with sampling rate:

$$ I_{DD} = 150 \mu A \text{ (at 8 SPS)} \quad \text{to} \quad 900 \mu A \text{ (at 860 SPS)} $$

An auto-shutdown mode reduces standby current to 0.5 μA.

Comparator Mode for Threshold Detection

The window comparator operates in two modes:

The ALERT/RDY pin asserts when conversions exceed programmable limits, enabling interrupt-driven designs.

1.3 Typical Applications in Voltage Measurement

High-Precision Sensor Interfaces

The ADS1115's 16-bit resolution and programmable gain amplifier (PGA) make it ideal for interfacing with low-voltage sensors. Strain gauges, thermocouples, and piezoelectric transducers often produce signals in the millivolt range. The PGA allows amplification of these signals before digitization, minimizing quantization errors. For example, a Wheatstone bridge output of ±10 mV can be amplified with a gain of 16 (PGA setting), mapping the signal to nearly full-scale on the ADC.

$$ V_{out} = \frac{V_{in} \times R_3}{R_1 + R_3} - \frac{V_{in} \times R_4}{R_2 + R_4} $$

Battery Monitoring Systems

In lithium-ion battery stacks, cell voltages must be measured with ±1 mV accuracy to ensure safe operation. The ADS1115's differential input mode eliminates ground loop errors when measuring individual cells in series. A voltage divider scales the cell voltage (typically 2.5–4.2 V) to within the ADC's input range (0–4.096 V at PGA=1). The I²C interface enables daisy-chaining multiple ADS1115s for monitoring high-voltage packs.

Cell 1 Cell 2 Cell N

Industrial Process Control

4–20 mA current loops are ubiquitous in industrial instrumentation. The ADS1115 measures the voltage across a precision shunt resistor (e.g., 250 Ω) to convert the current signal. With a 0.1% tolerance shunt, the system achieves better than 0.5% end-to-end accuracy. The ADC's built-in comparator can trigger alerts when values exceed programmable thresholds, enabling real-time fault detection.

Noise Mitigation Techniques

In electrically noisy environments, the ADS1115's data rate can be reduced to 8 SPS while enabling the low-noise PGA. Combining this with twisted-pair wiring and RC filters (cutoff frequency below Nyquist) improves SNR. For example, a 10 Hz first-order filter with:

$$ f_c = \frac{1}{2\pi RC} $$

reduces high-frequency noise by 20 dB/decade while preserving signal integrity.

Research Instrumentation

Physics experiments often require synchronous multi-channel measurements. The ADS1115's auto-conversion mode allows cycling through four channels at 860 SPS, with timestamps synchronized via an external trigger pin. This is particularly useful in:

# Example: Synchronized 4-channel readout
from ADS1115 import ADS1115
adc = ADS1115(i2c_addr=0x48)
adc.set_conv_mode('continuous')
adc.set_mux('diff_0_1')  # Ch0-Ch1
voltage1 = adc.read_voltage()
adc.set_mux('diff_2_3')  # Ch2-Ch3
voltage2 = adc.read_voltage()

2. Required Components and Tools

2.1 Required Components and Tools

Core Hardware Components

The ADS1115 is a 16-bit precision analog-to-digital converter (ADC) with an I²C interface, capable of resolving differential or single-ended voltages up to ±6.144 V. To achieve accurate measurements, the following components are essential:

Supporting Circuitry

To mitigate errors and protect the ADC:

$$ f_c = \frac{1}{2\pi RC} $$

Measurement Tools

Software Requirements

ADS1115 Module AIN0 AIN1

Wiring the ADS1115 to the Microcontroller

The ADS1115 is a 16-bit analog-to-digital converter (ADC) that communicates via the I²C protocol, making it compatible with most microcontrollers. Proper wiring is critical to ensure accurate voltage measurements and minimize noise interference. Below is a step-by-step guide to connecting the ADS1115 to a microcontroller, such as an Arduino or Raspberry Pi.

Power Supply Connections

The ADS1115 operates at a supply voltage (VDD) between 2.0V and 5.5V. For optimal performance:

I²C Communication Wiring

The ADS1115 uses I²C for data transfer, requiring two bidirectional lines:

For microcontrollers with multiple I²C buses, ensure the correct bus is selected in software. Pull-up resistors (typically 2.2kΩ–10kΩ) are required on both SCL and SDA lines to stabilize communication.

Address Configuration

The ADS1115 supports four I²C addresses (0x48–0x4B) set via the ADDR pin:

Input Channel Connections

The ADS1115 provides four single-ended or two differential input channels (A0–A3). For voltage measurement:

Noise Reduction Techniques

To minimize noise in high-precision applications:

Example Wiring Diagram

The following diagram illustrates a typical ADS1115-to-microcontroller connection:

ADS1115 VDD GND SCL SDA Microcontroller 3.3V GND SCL SDA

Mathematical Considerations

The ADS1115's resolution is determined by its 16-bit output and input voltage range. The voltage per least significant bit (LSB) is given by:

$$ V_{LSB} = \frac{V_{FSR}}{2^{16} - 1} $$

where VFSR is the full-scale range (e.g., ±6.144V). For a differential measurement between A0 and A1, the output code N relates to the input voltage VIN as:

$$ V_{IN} = N \times V_{LSB} $$
ADS1115 to Microcontroller Wiring Diagram Schematic diagram showing wiring connections between ADS1115 ADC and a microcontroller, including power, ground, I²C lines, and analog inputs. ADS1115 VDD GND SCL SDA A0 A1 A2 A3 Microcontroller 3.3V/5V GND SCL SDA 4.7kΩ 4.7kΩ 0.1µF VDD (3.3V/5V) GND SCL SDA
Diagram Description: The diagram would physically show the wiring connections between the ADS1115 and the microcontroller, including power, ground, I²C lines, and input channels.

2.3 Connecting Voltage Sources to the ADS1115

Input Voltage Range and PGA Configuration

The ADS1115 features a programmable gain amplifier (PGA) that allows measurement of differential or single-ended voltages across several ranges: ±6.144V, ±4.096V, ±2.048V, ±1.024V, ±0.512V, and ±0.256V. The PGA setting directly affects both the resolution and input impedance of the ADC. For a given full-scale range FSR, the least significant bit (LSB) size is:

$$ LSB = \frac{FSR}{2^{15}-1} $$

For example, in ±4.096V mode, the LSB resolution becomes 125μV. The input impedance Zin is dominated by the PGA's switched-capacitor architecture, typically presenting 6MΩ in parallel with 10pF when the PGA is enabled.

Differential vs. Single-Ended Measurements

The ADS1115 supports four single-ended or two differential input configurations through channels A0-A3. For differential measurements, the valid common-mode voltage range is constrained by:

$$ V_{CM} = \frac{V_{AINP} + V_{AINN}}{2} $$

must satisfy VSS + 0.3V ≤ VCM ≤ VDD - 0.3V. Exceeding these limits activates internal protection diodes, potentially distorting measurements.

Voltage Divider Networks for High Voltages

When measuring voltages beyond the PGA's maximum range, a precision resistor divider network should be implemented. The divider ratio α must account for both the attenuation factor and the loading effect on the source:

$$ \alpha = \frac{R_2}{R_1 + R_2} \times \frac{1}{1 + \frac{R_1||R_2}{Z_{source}}} $$

For minimal loading error, select resistors such that R1 + R2 is at least 100× the source impedance. Metal-film resistors with 0.1% tolerance or better are recommended to maintain accuracy across temperature variations.

Input Protection and Filtering

Transient voltage suppression (TVS) diodes should be placed between each input and ground, with a breakdown voltage slightly above the maximum expected input. An RC filter with cutoff frequency:

$$ f_c = \frac{1}{2\pi R_{filter}C_{filter}} $$

set to 1/10th of the sampling rate prevents aliasing while maintaining signal integrity. For 860SPS operation, 1kΩ and 100nF components yield a 1.59kHz cutoff.

PCB Layout Considerations

Route analog inputs as symmetric differential pairs with guard rings around high-impedance nodes. Maintain at least 4× trace width spacing between digital and analog signals. Place bypass capacitors (10μF tantalum + 100nF ceramic) within 5mm of the ADS1115's supply pins.

3. Setting the Gain and Input Range

3.1 Setting the Gain and Input Range

The ADS1115 programmable gain amplifier (PGA) allows adjusting the input voltage range by configuring the gain setting (FSR, Full-Scale Range). This is critical for optimizing resolution and avoiding saturation when measuring small or large signals. The gain is set via the Config Register (address 0x01) bits [11:9] (PGA[2:0]).

Gain Settings and Corresponding Input Ranges

The ADS1115 supports six gain settings, each defining a specific full-scale input voltage range:

PGA Setting (PGA[2:0]) Full-Scale Range (FSR) LSB Size (16-bit)
000 ±6.144 V 187.5 µV
001 ±4.096 V 125 µV
010 ±2.048 V 62.5 µV
011 ±1.024 V 31.25 µV
100 ±0.512 V 15.625 µV
101, 110, 111 ±0.256 V 7.8125 µV

Mathematical Derivation of LSB Size

The voltage resolution per least significant bit (LSB) is derived from the full-scale range (FSR) and the ADC's 16-bit resolution:

$$ \text{LSB Size} = \frac{\text{FSR}}{2^{15}} $$

For example, with PGA=010 (±2.048 V):

$$ \text{LSB Size} = \frac{4.096\,\text{V}}{32768} = 125\,\mu\text{V} $$

Practical Considerations

Code Example: Configuring Gain in Arduino


#include <Wire.h>
#include <Adafruit_ADS1X15.h>

Adafruit_ADS1115 ads;

void setup() {
  ads.begin();
  // Set gain to ±1.024V (PGA=011)
  ads.setGain(GAIN_ONE); 
}

void loop() {
  int16_t adc = ads.readADC_SingleEnded(0);
  float voltage = ads.computeVolts(adc);
}

For GAIN_TWOTHIRDS (±6.144 V), the ADC output saturates at 32767 for inputs ≥6.144 V. Always select the smallest FSR that accommodates the expected signal.

Configuring the I2C Communication

The ADS1115 communicates via the I2C (Inter-Integrated Circuit) protocol, a synchronous, multi-master, multi-slave serial bus standard. Proper configuration of I2C parameters ensures reliable data transfer between the ADC and the host microcontroller. Key parameters include clock speed, addressing, and pull-up resistor selection.

I2C Clock Speed Configuration

The ADS1115 supports standard-mode (100 kHz) and fast-mode (400 kHz) I2C operations. The clock speed is determined by the host microcontroller's I2C peripheral settings. For most applications, 400 kHz provides sufficient bandwidth while maintaining signal integrity. The rise time (tr) of the SDA and SCL signals must satisfy:

$$ t_r \leq 0.3 \cdot t_{low} $$

where tlow is the low period of the clock signal. For a 400 kHz clock (tlow = 1.3 µs), the maximum allowable rise time is 390 ns. This constrains the pull-up resistor value Rp:

$$ R_p \leq \frac{t_r}{C_b \cdot \ln\left(\frac{V_{DD}}{V_{DD} - 0.3V_{IL}}\right)} $$

where Cb is the bus capacitance (typically 100–400 pF) and VIL is the input low voltage threshold (0.3·VDD). For VDD = 3.3 V and Cb = 200 pF, Rp ≤ 2.2 kΩ.

Device Addressing

The ADS1115 features a configurable 7-bit I2C address set by the ADDR pin. The base address is 0x48 (10010002), with three additional options (0x49, 0x4A, 0x4B) selectable via ADDR pin grounding or connection to VDD or SDA/SCL. Multiple ADS1115s can share a bus by assigning unique addresses.

Register Map and Configuration

Communication occurs through four 16-bit registers:

The Config Register (0x01) is structured as follows:


// ADS1115 Config Register Structure (Big-Endian)
typedef union {
   struct {
      uint16_t OS      :1;  // Operational status/single-shot start
      uint16_t MUX     :3;  // Input multiplexer configuration
      uint16_t PGA     :3;  // Programmable gain amplifier setting
      uint16_t MODE    :1;  // Continuous/conversion mode
      uint16_t DR      :3;  // Data rate (samples per second)
      uint16_t COMP_MODE:1; // Comparator mode (traditional/window)
      uint16_t COMP_POL:1;  // Comparator polarity
      uint16_t COMP_LAT:1;  // Latching comparator
      uint16_t COMP_QUE:2;  // Comparator queue/disable
   };
   uint16_t value;
} ADS1115Config;

Initialization Sequence

A typical I2C initialization sequence involves:

  1. Asserting a start condition.
  2. Transmitting the device address + write bit (0x90 for address 0x48).
  3. Writing the Config Register address (0x01).
  4. Writing the high and low bytes of the Config Register.
  5. Asserting a stop condition.

For a single-shot conversion at 860 SPS with ±4.096 V range, the Config Register value is 0xC3E3 (11000011111000112).

Error Handling

Common I2C errors include clock stretching timeouts (tTIMEOUT > 25 ms) and arbitration loss. Implement retry logic with exponential backoff for robust operation. The ADS1115's internal oscillator ensures clock stretching does not exceed 8 ms during conversions.

3.3 Sampling Rate and Data Accuracy Considerations

The ADS1115's programmable sampling rate directly influences measurement resolution, noise performance, and power consumption. The device supports data rates from 8 SPS to 860 SPS, configurable through the DR[2:0] bits in the config register. Higher rates reduce integration time, increasing noise but enabling faster signal capture.

Sampling Rate vs. Noise Tradeoff

The effective number of bits (ENOB) follows:

$$ \text{ENOB} = N - \log_2 \left( \frac{V_{\text{noise,rms}}}{V_{\text{LSB}}}} \right) $$

where N is the nominal 16-bit resolution and Vnoise,rms is the input-referred noise. At 860 SPS, broadband noise dominates, reducing ENOB to ~14.5 bits. For low-frequency signals, 8 SPS yields near-full 16-bit resolution by averaging out thermal noise.

Aliasing and Anti-Aliasing Requirements

The Nyquist criterion demands:

$$ f_s > 2f_{\text{max}} $$

where fs is the sampling rate and fmax is the highest frequency component. Without external anti-aliasing filters, input signals above fs/2 will fold back into the measurement bandwidth. A first-order RC filter with cutoff:

$$ f_c = \frac{1}{2\pi RC} \ll \frac{f_s}{2} $$

is typically sufficient for most applications.

Power Supply Rejection Ratio (PSRR)

The ADS1115's PSRR of 85 dB at DC ensures stable measurements despite supply variations. However, high sampling rates increase current draw, potentially coupling supply noise. The relationship between sampling rate (fs) and supply current (IDD) is:

$$ I_{DD} = 150\mu\text{A} + (0.5\mu\text{A/SPS}) \times f_s $$

Bypass capacitors (10μF tantalum + 0.1μF ceramic) within 5mm of the device are critical for maintaining PSRR at maximum data rates.

Differential vs. Single-Ended Mode Tradeoffs

In differential mode, the ADS1115 rejects common-mode noise but halves the input range (±2.048V vs 0-4.096V single-ended). The common-mode rejection ratio (CMRR) degrades by ~10dB at 860 SPS compared to 8 SPS due to reduced settling time.

Aliasing Effect and Anti-Aliasing Filter Response Frequency-domain plot showing input signal spectrum, sampled spectrum with aliased components, and an RC filter frequency response with attenuation curve. Frequency (Hz) Amplitude Original Signal Sampled Signal f_s/2 f_max Aliased Lobes Signal Spectrum with Aliasing Frequency (Hz) Attenuation (dB) Filter Response f_c f_s/2 -20dB/decade Anti-Aliasing Filter Response Aliasing Effect and Anti-Aliasing Filter Response
Diagram Description: The section discusses aliasing and anti-aliasing filters, which are fundamentally visual concepts involving frequency domains and signal behavior.

4. Reading Raw Data from the ADS1115

Reading Raw Data from the ADS1115

The ADS1115 is a 16-bit analog-to-digital converter (ADC) with an I²C interface, capable of resolving small voltage differences with high precision. Reading raw data from the ADS1115 involves configuring its registers, initiating conversions, and interpreting the resulting binary output.

Register Configuration

The ADS1115 operates based on three primary registers: the Config Register, the Conversion Register, and the Threshold Registers. The Config Register (address 0x01) controls the ADC's operational parameters, including:

A typical Config Register setup for single-shot mode, ±4.096V range, and 128SPS would be:

$$ \text{Config} = 0b11000011 \quad 0b10000011 $$

Reading the Conversion Register

The Conversion Register (address 0x00) stores the most recent ADC result as a 16-bit two's complement value. The raw data can be read via I²C after setting the Config Register's OS bit to initiate a conversion. The ADC signals completion by resetting the OS bit.

The raw output (D) relates to the input voltage (VIN) and PGA gain (G) as:

$$ D = \frac{V_{IN} \times 32767}{G \times V_{\text{REF}}}} $$

where VREF is the internal reference voltage (4.096V). For example, a reading of 16384 corresponds to:

$$ V_{IN} = \frac{16384 \times 4.096}{32767} \approx 2.048 \text{V} $$

Practical Implementation

In embedded systems, the I²C transaction sequence involves:

  1. Writing to the Config Register to set the conversion parameters.
  2. Polling the OS bit or waiting for a conversion-ready interrupt.
  3. Reading the Conversion Register to obtain the raw 16-bit value.

The following Python snippet demonstrates this process using the smbus2 library:

import smbus2
import time

bus = smbus2.SMBus(1)
address = 0x48

# Configure ADS1115 for single-shot mode, A0 input, ±4.096V, 128SPS
config = [0xC3, 0x83]
bus.write_i2c_block_data(address, 0x01, config)

# Wait for conversion (poll OS bit)
while True:
    status = bus.read_byte_data(address, 0x01)
    if not (status & 0x80):
        break

# Read conversion result
raw_data = bus.read_i2c_block_data(address, 0x00, 2)
value = (raw_data[0] << 8) | raw_data[1]

Error Sources and Mitigation

Key error contributors in raw data acquisition include:

4.2 Converting Raw Data to Voltage Values

The ADS1115 outputs a 16-bit signed integer representing the measured voltage, which must be converted into a meaningful physical quantity. The conversion process depends on the programmable gain amplifier (PGA) setting and the reference voltage.

Raw ADC Output Representation

The ADC produces a 16-bit two's complement value, ranging from -32768 to +32767 for differential measurements or 0 to 32767 for single-ended measurements. The relationship between the raw value and input voltage is linear:

$$ V_{in} = \frac{\text{Code} \times \text{FSR}}{2^{15} - 1} $$

where Code is the raw ADC value, and FSR is the full-scale range determined by the PGA gain setting.

Full-Scale Range Calculation

The FSR is defined by the selected PGA gain (PGA_GAIN), which amplifies the input signal before digitization. The available gain settings and corresponding FSR values are:

The FSR can be expressed as:

$$ \text{FSR} = \frac{V_{\text{ref}}}{\text{PGA\_GAIN}} $$

where Vref is the internal reference voltage (typically 4.096V).

Practical Conversion Formula

Combining these relationships, the voltage corresponding to a raw ADC value is:

$$ V_{in} = \frac{\text{Code} \times V_{\text{ref}}}{\text{PGA\_GAIN} \times (2^{15} - 1)} $$

For single-ended measurements, the formula simplifies since the code is always positive:

$$ V_{in} = \frac{\text{Code} \times V_{\text{ref}}}{\text{PGA\_GAIN} \times (2^{15} - 1)} $$

For differential measurements, negative values represent inverted polarity:

$$ V_{in} = \frac{\text{Code} \times V_{\text{ref}}}{\text{PGA\_GAIN} \times (2^{15} - 1)} $$

Implementation Example

Consider a differential measurement with PGA_GAIN = 2 (±2.048V range) and a raw reading of 16384. The corresponding voltage would be:

$$ V_{in} = \frac{16384 \times 4.096}{2 \times 32767} \approx 1.024 \text{V} $$

This calculation accounts for both the scaling introduced by the PGA and the ADC's resolution.

Error Sources and Calibration

Several factors can affect measurement accuracy:

For precision applications, a two-point calibration (zero and full-scale) can compensate for these errors. The corrected voltage becomes:

$$ V_{corrected} = (V_{raw} - \text{Offset}) \times \text{Gain\_Factor} $$

where Offset and Gain_Factor are determined during calibration.

4.3 Handling Negative Voltages and Differential Measurements

The ADS1115 is a 16-bit ADC capable of measuring both single-ended and differential voltages, including negative voltages relative to its reference. Understanding its input configuration and mathematical representation is critical for accurate measurements in bipolar applications.

Differential Input Configuration

The ADS1115 provides four input channels (A0-A3) that can be configured as two differential pairs (A0-A1, A2-A3) or four single-ended inputs. In differential mode, the ADC measures the voltage difference between two pins:

$$ V_{diff} = V_{IN+} - V_{IN-} $$

where VIN+ and VIN- are the voltages at the positive and negative input pins respectively. The differential measurement rejects common-mode noise, making it ideal for low-voltage signals in noisy environments.

Negative Voltage Measurement

The ADS1115 can measure negative differential voltages within its programmable gain amplifier (PGA) range. The ADC output is represented in two's complement format, allowing direct interpretation of positive and negative values:

$$ V_{measured} = \frac{Code \times FS}{2^{15} - 1} $$

where FS is the full-scale range determined by the PGA setting (e.g., ±6.144V, ±4.096V, etc.), and Code is the signed 16-bit ADC reading. For example, a reading of -16384 with ±4.096V range corresponds to:

$$ V = \frac{-16384 \times 4.096V}{32767} \approx -2.048V $$

Practical Implementation

When measuring bipolar signals, ensure:

For floating signal sources, bias one input to mid-supply using a voltage divider to maintain common-mode requirements. The differential measurement will still accurately capture the voltage difference while keeping both inputs within the valid range.

Noise Considerations

Differential measurements provide inherent common-mode rejection, but proper grounding and shielding remain essential. For optimal performance:

The ADS1115's internal PGA and oversampling capabilities allow resolution down to 188μV at ±6.144V range, making it suitable for precise differential measurements in instrumentation and sensor interfaces.

ADS1115 Differential Input Configuration and Voltage Ranges Diagram showing differential input configuration (A0-A1), PGA block, and common-mode voltage range boundaries for ADS1115 ADC. A0 (VIN+) A1 (VIN-) Differential Voltage PGA Gain: ±6.144V (Configurable) VIN (V) Common Mode (V) VDD GND Valid Common Mode Range 0V to VDD+0.3V VDD: 2.0V to 5.5V GND: 0V
Diagram Description: The diagram would physically show the differential input configuration and common-mode voltage range boundaries.

5. Debugging I2C Communication Problems

5.1 Debugging I2C Communication Problems

When interfacing the ADS1115 with a microcontroller via I2C, communication failures can arise due to electrical, timing, or addressing issues. Diagnosing these problems requires a systematic approach, leveraging both theoretical understanding and practical debugging tools.

Common I2C Failure Modes

The I2C protocol is susceptible to several failure modes, each with distinct symptoms:

$$ R_{p} < \frac{V_{DD} - 0.4V}{3mA} $$

where VDD is the supply voltage. For 3.3V systems, this yields Rp < 966Ω. Excessive capacitance (Cbus) beyond 400pF violates rise time specifications, requiring stronger pull-ups or bus buffers.

Diagnostic Methodology

A structured debugging approach involves:

  1. Signal inspection: Use an oscilloscope to verify SDA/SCL waveforms. Valid I2C signals should exhibit clean transitions with < 300ns rise/fall times at 100kHz. Ringing or excessive overshoot indicates impedance mismatches.
  2. Bus probing: Measure DC voltages:
    • SDA and SCL should idle at VDD
    • Voltage levels below 0.8VDD during transmission suggest weak pull-ups
  3. Protocol analysis: Capture transactions with a logic analyzer. A valid ADS1115 read sequence should show:
    • Start condition (SDA falling while SCL high)
    • 7-bit address + R/W bit (0x48 + 1 for read)
    • Register pointer byte
    • Repeated start with read sequence

Advanced Debugging Techniques

For persistent issues, employ these methods:

$$ V_{OL} = R_{p} \times I_{OL} $$

where IOL is the device's maximum low-level output current (1.5mA per I2C specification).


  #include <Wire.h>
  
  void setup() {
    Wire.begin();
    Serial.begin(9600);
    for(uint8_t addr = 8; addr < 120; addr++) {
      Wire.beginTransmission(addr);
      if(Wire.endTransmission() == 0) {
        Serial.print("Device found at 0x");
        Serial.println(addr, HEX);
      }
    }
  }

Case Study: Rise Time Violation

A 3.3V system with 1kΩ pull-ups and 300pF bus capacitance exhibits tr = 0.847 × Rp × Cbus = 254ns, within specification. However, adding 150pF of probe capacitance pushes tr to 381ns, potentially causing timeouts. This demonstrates the need for low-capacitance probing or active buffering during debugging.

I2C Signal Integrity Analysis A combined waveform and schematic diagram showing I2C signal integrity with SDA/SCL waveforms, pull-up resistors, bus capacitance, microcontroller, and ADS1115. I2C Signal Waveforms Time V V_DD V_OL SCL SDA t_r I2C Bus Schematic MCU ADS1115 Rp Rp V_DD C_bus SCL SDA SCL SDA
Diagram Description: The section discusses I2C signal integrity and timing specifications, which require visualization of waveform characteristics and bus topology.

5.2 Addressing Noise and Signal Integrity Issues

Noise Sources in High-Precision ADC Measurements

When measuring voltage with the ADS1115, noise can arise from multiple sources, including:

$$ V_n = \sqrt{4k_B T R \Delta f} $$

where \( k_B \) is Boltzmann's constant, \( T \) is temperature in Kelvin, \( R \) is resistance, and \( \Delta f \) is the bandwidth.

$$ I_n = \sqrt{2q I \Delta f} $$

where \( q \) is the electron charge.

Quantifying Noise in the ADS1115

The ADS1115's effective number of bits (ENOB) is degraded by noise. The signal-to-noise ratio (SNR) for a sinusoidal input is:

$$ \text{SNR} = 6.02 \cdot N + 1.76 + 10 \log_{10} \left( \frac{f_s}{2 \Delta f} \right) $$

where \( N \) is the nominal resolution (16 bits), \( f_s \) is the sampling rate, and \( \Delta f \) is the bandwidth. For DC measurements, low-frequency \( 1/f \) noise dominates.

Mitigation Strategies

Hardware Techniques

$$ f_c = \frac{1}{2 \pi R C} $$

Software Techniques

Case Study: Reducing Noise in a Thermocouple Measurement

In a high-gain thermocouple amplifier (e.g., 1000×) feeding the ADS1115:

Noise Spectrum Before Filtering
Noise Spectrum Comparison Before and After Filtering Side-by-side comparison of unfiltered and filtered noise spectra with an RC filter schematic below. Shows frequency (Hz) vs amplitude (dB) with 10Hz cutoff and 40dB attenuation. Noise Spectrum Comparison Before and After Filtering 0 dB -20 dB -40 dB -60 dB -80 dB Amplitude (dB) 1 10 100 1k 10k Frequency (Hz) 10Hz cutoff Unfiltered Filtered 40dB attenuation R=1kΩ C=16μF Input Output
Diagram Description: The section discusses noise reduction techniques and includes a case study with specific filter components and noise spectrum changes, which would benefit from a visual comparison of noise before and after filtering.

5.3 Calibration and Accuracy Improvements

The ADS1115 provides high-resolution analog-to-digital conversion, but its accuracy depends on proper calibration and mitigation of error sources. Systematic errors arise from gain drift, offset voltage, and reference voltage instability, while random errors stem from thermal noise and quantization effects.

Offset and Gain Calibration

The ADC's transfer function is given by:

$$ V_{out} = G \cdot (V_{in} + V_{offset}) $$

where G is the gain and Voffset is the input-referred offset. A two-point calibration corrects both parameters:

  1. Apply zero input voltage and measure the output code C0.
  2. Apply a known reference voltage Vref and measure Cref.

The calibrated output is then:

$$ V_{cal} = \frac{V_{ref}}{C_{ref} - C_0} \cdot (C_{raw} - C_0) $$

Reference Voltage Stability

The internal 2.048V reference has ±0.05% initial accuracy but drifts with temperature (5ppm/°C typical). For precision applications:

$$ V_{ref}(T) = V_{ref0} \cdot (1 + \alpha \cdot \Delta T) $$

Noise Reduction Techniques

The effective number of bits (ENOB) is reduced by noise. Strategies include:

The noise-limited resolution follows:

$$ \sigma_V = \frac{V_{FSR}}{2^N \sqrt{12}} \sqrt{1 + 4 \frac{f_{Nyquist}}{f_{cutoff}}} $$

PCB Layout Considerations

Proper board design minimizes interference:

Signal ADS1115 MCU

Dashed lines indicate analog signal paths requiring special care.

ADS1115 Calibration and PCB Layout Schematic diagram of ADS1115 calibration setup and PCB layout, showing signal flow from source to MCU with analog and digital traces. GND Plane Signal Source ADS1115 V_ref MCU Analog Traces Digital Lines Bypass Caps Signal Flow Key: Analog Digital Bypass Cap
Diagram Description: The section includes complex calibration procedures and PCB layout considerations that benefit from visual representation of signal paths and component placement.

6. Using Multiple ADS1115 Modules

6.1 Using Multiple ADS1115 Modules

When high-channel-count voltage measurements are required, multiple ADS1115 modules can be interfaced on the same I²C bus. The ADS1115 supports configurable I²C addresses through its ADDR pin, allowing up to four modules to operate simultaneously on a single bus without address conflicts.

Address Configuration and I²C Bus Topology

The ADS1115 provides four possible I²C addresses determined by the voltage applied to its ADDR pin:

For optimal signal integrity, keep I²C trace lengths below 30 cm and use 4.7 kΩ pull-up resistors (standard for 3.3V operation). When operating at higher bus speeds (≥ 400 kHz), reduce pull-up values proportionally to maintain sharp signal edges:

$$ R_{pull-up} = \frac{t_r}{0.8473 \cdot C_{bus}} $$

where tr is the desired rise time (typically ≤ 300 ns for 400 kHz) and Cbus is the total bus capacitance.

Synchronization Considerations

When sampling correlated signals across multiple ADS1115s, the internal oscillators' 2% frequency tolerance introduces phase drift. For time-coherent measurements:

Data Acquisition Timing Analysis

The total throughput for N modules depends on the programmed data rate fs and I²C clock frequency fSCL:

$$ T_{total} = N \left( \frac{1}{f_s} + \frac{34}{f_{SCL}} \right) $$

where 34 clock cycles account for the I²C transaction overhead (7-bit address + register pointer + 16-bit data transfer). At the maximum 860 SPS with 400 kHz I²C, four modules achieve an aggregate sampling rate of 3.44 kSPS.

Noise and Crosstalk Mitigation

When stacking multiple ADCs, observe these precautions:

Advanced Configuration Example

This Python snippet demonstrates synchronized operation of two ADS1115 modules at 3300 SPS, with the second module's input referenced to the first module's output:

import board
import adafruit_ads1x15.ads1115 as ADS
from adafruit_ads1x15.analog_in import AnalogIn

i2c = board.I2C()
ads1 = ADS.ADS1115(i2c, address=0x48)  # Reference module
ads2 = ADS.ADS1115(i2c, address=0x49)  # Measurement module

# Configure both modules for synchronized sampling
ads1.data_rate = 3300
ads2.data_rate = 3300
ads1.mode = ADS.Mode.CONTINUOUS
ads2.mode = ADS.Mode.CONTINUOUS

# Set up ratiometric measurement
ref_chan = AnalogIn(ads1, ADS.P0)
meas_chan = AnalogIn(ads2, ADS.P0)

def read_ratio():
    ref = ref_chan.voltage
    meas = meas_chan.voltage
    return (meas - ref) / ref

This configuration achieves 0.01% relative accuracy for ratiometric measurements by eliminating power supply drift effects.

Multi-ADS1115 I²C Bus Configuration Schematic diagram showing I²C bus topology with a microcontroller connected to four ADS1115 modules, including ADDR pin configurations and shared CONVST sync line. Microcontroller (e.g., Arduino) I²C Bus 4.7kΩ 4.7kΩ ADS1115 0x48 ADDR GND ADS1115 0x49 ADDR VDD ADS1115 0x4A ADDR SCL ADS1115 0x4B ADDR SDA CONVST Sync Input Sync Input Sync Input Sync Input Legend I²C Bus (SDA/SCL) CONVST Sync Line ADDR Pin
Diagram Description: The section involves I²C bus topology with multiple modules and synchronization methods, which are spatial concepts best shown visually.

6.2 Implementing Continuous Sampling Mode

The ADS1115 supports two sampling modes: single-shot and continuous. In continuous mode, the ADC automatically performs conversions at a fixed interval determined by the data rate setting, eliminating the need for repeated I2C trigger commands. This mode is optimal for real-time monitoring applications where latency must be minimized.

Configuring the Config Register

Continuous mode is enabled by setting the MODE bit (bit 8) in the config register to 0. The conversion process begins immediately after writing to the register. The data rate is controlled by bits 5:7 (DR[2:0]), which select sampling frequencies from 8 SPS to 860 SPS. For example, setting DR[2:0] = 100 (0x04) enables 128 SPS.

$$ t_{\text{sample}} = \frac{1}{\text{DR}} $$

where tsample is the sampling period and DR is the selected data rate.

Reading Data in Continuous Mode

The conversion-ready pin (ALERT/RDY) can be configured to signal when new data is available, reducing polling overhead. Alternatively, the OS bit (bit 15) can be monitored to check conversion status. The 16-bit result is stored in the conversion register (address 0x00) and must be read before the next conversion completes to avoid data loss.

Voltage Calculation

The raw ADC value (N) is converted to voltage using the full-scale range (FSR) and gain setting (PGA):

$$ V_{\text{in}} = \frac{N \cdot \text{FSR}}{2^{15} \cdot \text{PGA}} $$

For FSR = 4.096V and PGA = 1, a reading of 0x7FFF corresponds to +4.096V, while 0x8000 represents -4.096V.

Noise and Anti-Aliasing Considerations

At higher data rates, noise increases due to the reduced integration time. The effective number of bits (ENOB) drops as the sampling frequency approaches the ADS1115's bandwidth limit. An anti-aliasing filter with a cutoff frequency below half the sampling rate (Nyquist criterion) is recommended:

$$ f_c \leq \frac{\text{DR}}{2} $$

For 860 SPS, a first-order RC filter with fc ≤ 430 Hz is typical.

I2C Timing Constraints

Continuous mode imposes strict timing requirements on the I2C bus. At 860 SPS, conversions occur every 1.16 ms, leaving limited time for data retrieval. Use I2C clock stretching or DMA transfers to prevent buffer overflows in microcontroller applications.


// Example: Configuring ADS1115 for continuous mode at 128 SPS (Arduino)
#include <Wire.h>
#define ADS_ADDR 0x48

void setup() {
  Wire.begin();
  // Set MODE=0, DR=100 (128 SPS), PGA=2 (±2.048V)
  Wire.beginTransmission(ADS_ADDR);
  Wire.write(0x01); // Config register
  Wire.write(0b00000100); // Hi byte: OS=0, MUX=000, PGA=010, MODE=0
  Wire.write(0b10000011); // Lo byte: DR=100, COMP_*=000, DISCOMP=11
  Wire.endTransmission();
}

int16_t readADC() {
  Wire.beginTransmission(ADS_ADDR);
  Wire.write(0x00); // Conversion register
  Wire.endTransmission();
  Wire.requestFrom(ADS_ADDR, 2);
  return (Wire.read() << 8) | Wire.read();
}

6.3 Power Consumption Optimization Techniques

Dynamic Sampling Rate Adjustment

The ADS1115's power consumption scales with its sampling rate (fs), following the relationship:

$$ P_{ADC} = C_{load} V_{DD}^2 f_s + I_{static} V_{DD} $$

where Cload is the switched capacitance (typically 20 pF), VDD is the supply voltage, and Istatic is the quiescent current (150 µA typical). For battery-powered applications, implement adaptive sampling:

Programmable Gain Amplifier (PGA) Optimization

The integrated PGA contributes significantly to power dissipation. The current consumption IPGA follows:

$$ I_{PGA} = 0.5 \times 10^{-6} \times 2^{(G/6)} $$

where G is the gain setting in dB. Key strategies:

Supply Voltage Scaling

The ADS1115's digital power dissipation follows a quadratic relationship with supply voltage:

$$ P_{digital} \propto V_{DD}^2 $$

Practical implementation considerations:

Advanced Sleep Modes

The ADS1115 supports multiple low-power states with wake-up times critical for power-constrained applications:

Mode Current Wake-up Time
Active 150 µA 0 µs
Auto-Shutdown 0.5 µA 25 µs
Power-Down 0.1 µA 100 µs

Optimal sleep strategy involves:

Input Network Optimization

The external input network can significantly impact power budget:

$$ P_{input} = \frac{V_{in}^2}{R_{source} + R_{in}} $$

Design techniques include:

Clock Management

The internal oscillator current can be reduced by:

7. Official Datasheets and Documentation

7.1 Official Datasheets and Documentation

7.2 Recommended Tutorials and Guides

7.3 Community Forums and Support Resources