During normal' 'hold'' mode, the replicated analog voltage is buffered straight through the S/H amplifier to the output. Upon issuance of a SAMPLE signal, the S/H amplifier is placed in the hold mode, holding the voltage until the new analog voltage is valid. The same SAMPLE signal triggers an update to the input sample-and-hold amplifier. The most current analog voltage is captured and held for conversion. The previously determined voltage is held stable at the output during the conversion cycle while the SAR/D-to-A converter continuously adjusts to replicate the new input voltage.
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At the end of the conversion, the output sample-and-hold amplifier is once again placed in the track mode. The new analog voltage is then regenerated.
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