Posted on Aug 22, 2012

This simple circuit generates a dual-speed clock for personal computers. The circuit synchronizes your asynchronous switch inputs with the master clock to provide glitch-free transitions from one clock speed to the other. The dual-speed clock allows some programs to run at the higher clock speed in order to execute more quickly. Other programs- for example, programs that use loops for timing-can still run at the lower speed as necessary. The circuit will work with any master-clock frequency that meets the flip-flops minimumpulse- width specs.

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The two D two flip-flops, JC1 and IC2, and an XOR gate, IC3, form a binary divider that develops the 6- and 12-MHz clocks. When the NT signal is low, the reset pin forces the 6cMHz output low. On the other hand, when the NT signal is high, JC3 blocks the 12-MHz output. Therefore, only one of the two clock signals passes through JC3 and gets clocked into IC6. Because the master-elk signal clocks IC6, asynchronous switching of the NT signal can"t generate an output pulse shorter than 41 p.s (1/24 MHz). Also, the synchronization eliminates glitches.

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