JEC-2 delay circuit diagram consisting of b


Posted on Dec 11, 2010

Delay application circuit is shown in Figure purposes JEC-2 consisting of two. When the input end is logic 0 to 1, the output also immediately end 1 ; but when the input end is


JEC-2 delay circuit diagram consisting of b
Click here to download the full size of the above Circuit.

high level 1 transition to low level 0, the output by the delay after it becomes 0, the delay time from 10 F capacitor charging to the trigger level to ask the decision. This circuit provides the delay time is 0.02 to 10 seconds, for the case where the delay time shorter. Change R and C, you can change the delay time. Re value adjustment, you can correct errors.




Leave Comment

characters left:

New Circuits

.

 


Popular Circuits

Proteus
Vlf Converter
Domestic VLF Reception
ve170 monitor repair with led
microphone amplifier 20khz 12v
Simple FM Transmitter circuit schematic Long range short range using VMR6512 Hi-Fi Audio FM transmitter module
Single 10 Shunt Fed Hartley Oscillator for 80 meter CW
TMB-1 Tri-Mode Buffer Amplifier Box
DSpace badge board build Instructions



Top