Microcontroller Timers and Counters: Definition and Core Concepts

Fundamental Operation

Timers and counters in microcontrollers are hardware peripherals designed to measure or generate precise time intervals. A timer increments its value at a fixed frequency derived from the system clock or an external oscillator, while a counter increments upon detecting edges on an external signal. Both operate on the principle of a n-bit register that overflows after reaching its maximum value (2ⁿ - 1).

Mathematical Basis

The time resolution of a timer is determined by its input clock frequency (f_clk) and prescaler (P):

For a 16-bit timer with f_clk = 16 MHz and P = 8, the maximum measurable interval before overflow is:

Modes of Operation

• Timer Mode: Clock-driven increments for PWM generation or delay creation
• Counter Mode: Edge-triggered increments for frequency measurement
• Capture Mode: Records timer value upon external trigger
• Compare Mode: Generates interrupts or toggles outputs at specific values

Hardware Implementation

Modern microcontrollers integrate multiple timer units with:

• Dedicated clock multiplexers for flexible source selection
• Auto-reload registers for periodic interrupt generation
• Daisy-chaining capability for extended resolution

Practical Applications

In motor control systems, timers generate precisely timed PWM signals with dead-band insertion. Counters in industrial automation precisely measure encoder pulses for position tracking, with typical resolutions down to 50 ns in 32-bit implementations.

Advanced Features

High-end timer peripherals support:

• Quadrature decoding for rotary encoders
• Hall sensor pattern detection
• Linked DMA operations for low-latency data transfer

1.2 Differences Between Timers and Counters

Fundamental Operational Modes

Timers and counters in microcontrollers both rely on incrementing a register, but their triggering mechanisms differ fundamentally. A timer increments its value at a fixed frequency derived from the microcontroller's clock signal, making it a function of time. For example, a 16-bit timer with a 1 MHz clock increments every 1 µs, overflowing after 65.536 ms. The relationship between clock frequency (f_clk) and timer resolution (Δt) is:

In contrast, a counter increments only upon receiving an external pulse at a dedicated input pin, independent of the system clock. This makes it suitable for event-driven applications like measuring RPM or counting objects on a conveyor belt.

Clock Source and Signal Dependency

Timers are synchronized with the internal clock, which may be prescaled to adjust resolution. For instance, an 8 MHz clock with a prescaler of 8 yields an effective timer clock of 1 MHz. The prescaler value (N) modifies the timer increment rate:

Counters, however, operate asynchronously, responding to edges (rising or falling) of an external signal. This introduces considerations for signal debouncing and noise immunity, often requiring hardware or software filtering.

Applications and Practical Use Cases

• Timers: PWM generation, real-time task scheduling, baud rate generation.
• Counters: Quadrature encoder decoding, pulse accumulation, frequency measurement.

Hardware Implementation

Timer peripherals often include auxiliary features like:

• Compare/capture registers for triggering interrupts or PWM.
• Auto-reload modes for periodic tasks.

Counters typically lack these features but may support gate control, where an enable signal validates external pulses.

Mathematical Modeling

The maximum countable time (T_max) for an n-bit timer is:

For a counter, the maximum count (C_max) is simply:

Overflow handling differs: timers often trigger interrupts, while counters may latch values or generate hardware events.

Edge Cases and Error Sources

Timers suffer from jitter due to clock drift or interrupt latency, while counters face missed pulses from signal glitches. Advanced microcontrollers mitigate these with:

• Timer synchronization circuits (e.g., shadow registers).
• Counter noise cancellation (e.g., minimum pulse-width validation).

1.3 Common Applications in Embedded Systems

Precision Timing and Event Scheduling

Microcontroller timers are fundamental in generating precise time delays and scheduling real-time tasks. A timer configured in interval mode generates periodic interrupts, enabling deterministic execution of time-critical functions. The interrupt period T is derived from the timer clock frequency f_timer and the prescaler N:

where TOP is the timer's maximum count value (e.g., 0xFFFF for a 16-bit timer). Applications include:

• Real-time operating system (RTOS) task schedulers
• Sensor sampling at fixed intervals (e.g., ADC triggering)
• Timeout management in communication protocols

Pulse-Width Modulation (PWM) Generation

Timers with PWM output modes drive motors, LEDs, and power converters by varying duty cycle D:

where CCR is the capture/compare register value and ARR is the auto-reload register. Key implementations:

• Brushless DC motor control (6-step commutation)
• LED dimming with gamma correction
• Switch-mode power supply regulation

Frequency Measurement and Encoder Interfaces

Timer input capture modes measure external signal frequency f_ext by recording timestamps of edges:

Quadrature encoder interfaces use dual-edge detection to track position/speed in robotic systems. Advanced features include:

• Hall-effect sensor decoding for RPM measurement
• Optical encoder interpolation
• Resonant frequency tracking in ultrasonic systems

Waveform Generation and Signal Processing

Timers synchronize with DACs to produce arbitrary waveforms through direct memory access (DMA)-based buffer updates. The output frequency resolution is:

where n is the timer resolution. Applications include:

• Digital synthesizers (DDS algorithms)
• Impedance spectroscopy excitation signals
• Spread-spectrum clock generation

Time-Stamping and Data Logging

High-resolution timers (e.g., 32-bit @ 100MHz) provide µs-level timestamping for:

• Precision event sequencing in particle detectors
• Network packet arrival time tagging (PTP protocol)
• Inertial measurement unit (IMU) data synchronization

Timer Modes: Input Capture, Output Compare, PWM

Input Capture Mode

Input capture mode records the exact time at which an external event occurs, typically using a dedicated timer input pin. When a signal edge (rising or falling) is detected, the current timer value is latched into a capture register, allowing precise timestamping. The time difference between two events can be computed as:

where T_capture is the captured timer value and T_clock is the timer clock period. This mode is essential for frequency measurement, pulse-width analysis, and rotary encoder decoding.

Output Compare Mode

Output compare mode triggers actions (e.g., pin toggling, interrupt generation) when the timer counter matches a predefined value stored in a compare register. The compare register OCR determines the timing:

Applications include waveform generation, time-delay creation, and synchronized signal control. Advanced microcontrollers allow concatenated timers for extended resolution.

Pulse-Width Modulation (PWM) Mode

PWM generates variable-duty-cycle signals by periodically resetting the timer counter at a top value (TOP) and toggling outputs at compare matches. The duty cycle D is:

Key parameters include PWM frequency (f_PWM = f_clock/(TOP + 1)) and resolution (bits = log₂(TOP + 1)). High-resolution PWM is critical for motor control, LED dimming, and power converters.

PWM Generation Techniques

• Fast PWM: Counter resets at TOP, single compare point per period.
• Phase-Correct PWM: Counter counts up then down, reducing harmonic noise.
• Center-Aligned PWM: Symmetrical around TOP/2, used in motor drives.

Hardware Considerations

Timer peripherals often feature:

• Dead-time generators for H-bridge control
• Burst-mode PWM for reduced EMI
• DMA support for buffer updates without CPU intervention

2.2 Clock Sources and Prescalers

Clock Sources in Microcontroller Timers

Microcontroller timers rely on clock signals to increment their counters. The clock source determines the timer's resolution and accuracy. Common clock sources include:

• Internal oscillator – Typically provides a low-frequency clock (e.g., 32 kHz or 8 MHz) with moderate stability (±1–5%).
• External crystal oscillator – Delivers high-frequency, high-precision timing (e.g., 16 MHz with ±10–50 ppm stability).
• Phase-locked loop (PLL) – Multiplies the input clock frequency to achieve higher speeds (e.g., 80 MHz from a 16 MHz source).
• External clock input – Allows synchronization with an external signal, useful in distributed systems.

Prescalers and Frequency Division

A prescaler divides the input clock frequency before it reaches the timer counter, enabling longer timing intervals. The division factor (N) is typically a power of two (e.g., 1, 2, 4, ..., 256). The effective timer clock frequency (f_timer) is given by:

For example, a 16 MHz clock with a prescaler of 64 yields a timer frequency of 250 kHz. The timer resolution (Δt) then becomes:

Trade-offs in Prescaler Selection

Choosing an appropriate prescaler involves balancing resolution and maximum interval:

• High prescaler values – Increase maximum measurable interval but reduce resolution.
• Low prescaler values – Improve resolution but limit the maximum count before overflow.

For a 16-bit timer with a 16 MHz clock and prescaler of 8, the maximum interval before overflow is:

Dynamic Prescaler Adjustment

Some microcontrollers allow runtime prescaler modification, enabling adaptive timing resolution. However, this may introduce glitches if not synchronized properly. Techniques like double buffering ensure smooth transitions.

Clock Synchronization and Jitter

Asynchronous clock sources (e.g., external signals) require synchronization to the microcontroller's internal clock domain, introducing latency (±1–2 clock cycles). High-frequency jitter can degrade timing accuracy, particularly in precision applications like PWM generation.

Practical Considerations

• Power consumption – Higher clock frequencies increase dynamic power dissipation (P ∝ f_clock × V²).
• EMI reduction – Lowering clock frequencies via prescalers can mitigate electromagnetic interference.
• Real-time constraints – Critical tasks (e.g., motor control) may require dedicated timers with fixed prescalers to avoid runtime overhead.

2.3 Timer Interrupts and Event Generation

Timer interrupts enable microcontrollers to execute time-critical tasks without continuous polling. When a timer reaches a predefined value (e.g., overflow or compare match), it triggers an interrupt request (IRQ), diverting the CPU to an interrupt service routine (ISR). The latency between interrupt assertion and ISR execution depends on the microcontroller's interrupt controller architecture and current instruction pipeline state.

Interrupt Latency and Jitter

Interrupt latency (t_latency) comprises three components:

• t_sync: Synchronization delay (1-3 clock cycles) as the interrupt signal propagates through flip-flops.
• t_exec: Worst-case instruction completion time (e.g., multi-cycle multiply or divide).
• t_{isr_prologue}: Context-saving overhead (register pushes to stack).

Jitter (Δt) arises from variations in t_exec and is minimized by:

• Avoiding long-running atomic operations before ISRs.
• Using nested interrupts cautiously (priority-based controllers like NVIC in ARM Cortex-M).

Event Generation Without CPU Intervention

Advanced timer peripherals (e.g., STM32's TIM, AVR's TC1) support hardware-triggered events via:

• Output Compare Units: Automatically toggle/clear/set GPIO pins on compare matches.
• Input Capture: Record timestamps of external edges with nanosecond resolution.
• DMA Triggers: Transfer ADC results or buffer data without CPU overhead.

Practical Implementation: PWM Generation

For a 16-bit timer (e.g., TCA0 in ATmega4809), PWM frequency (f_PWM) and duty cycle (D) are set via:

where N is the prescaler (1, 2, 4, ..., 1024), and TOP is the counter's maximum value (e.g., 0xFFFF). An interrupt can be generated at the TOP or BOTTOM for synchronization.

// Configure PWM on ATmega4809 with 20% duty cycle
TCA0.SINGLE.CTRLA = TCA_SINGLE_CLKSEL_DIV16_gc | TCA_SINGLE_ENABLE_bm;
TCA0.SINGLE.PER = 9999;  // TOP value for 1kHz @ 16MHz/16
TCA0.SINGLE.CMP0 = 2000; // 20% duty cycle
TCA0.SINGLE.INTCTRL = TCA_SINGLE_OVF_bm; // Enable overflow interrupt
   

Real-World Considerations

• Race Conditions: Reading TCNT while updating CCR may cause glitches. Use buffered registers (e.g., ARM's TIMx_CCR1 shadow registers).
• Power Consumption: Timer interrupts prevent sleep modes. Use event-driven peripherals (e.g., CCL in AVR-Dx) for low-power designs.

3.1 Event Counting and Frequency Measurement

Microcontroller timers configured as counters operate by incrementing their register values in response to external signal edges. The counting mechanism relies on transitions detected on a designated input pin, typically synchronized with the microcontroller's clock domain to avoid metastability. Edge sensitivity—whether rising, falling, or both—is programmable in most modern architectures, allowing precise control over what constitutes a countable event.

Event Counting Modes

In edge-counting mode, the timer increments its count register (TCNTn) on each qualifying edge of an external signal. The maximum countable frequency is constrained by the synchronization logic and is generally half the timer's input clock frequency (Nyquist criterion). For a 16 MHz timer clock, this limits event counting to approximately 8 MHz without prescaling. The relationship between the input signal frequency (f_in) and the timer resolution is given by:

Higher frequencies require prescaling the input signal or using hardware capture units with dedicated signal conditioning circuits.

Frequency Measurement Techniques

Two primary methods exist for frequency measurement:

• Direct Period Measurement: The timer captures the duration between consecutive edges of the input signal using its internal clock. For a signal with period T_in, the timer value N relates to the input frequency as:

• Reciprocal Counting: The timer gates its counting period using the unknown signal as a timebase. By counting cycles of a known high-frequency reference clock during one period of the input signal, the frequency is calculated as:

Reciprocal counting offers superior accuracy for low-frequency signals, while direct period measurement excels at higher frequencies.

Error Sources and Mitigation

Quantization error arises from the discrete nature of timer clocks, introducing a ±1 count uncertainty. For a timer running at frequency f_timer, the worst-case relative error in period measurement is:

Synchronization delays between asynchronous input signals and the timer clock domain introduce additional phase uncertainty. Advanced microcontrollers mitigate this through:

• Clock dithering techniques
• Multiple-stage synchronization flip-flops
• Hardware averaging of multiple measurements

Practical Implementation

Modern microcontrollers like ARM Cortex-M devices implement combined timer/counter peripherals with hardware capture/compare units. For example, the STM32 series allows simultaneous capture of timer values on both rising and falling edges, enabling pulse-width measurement without software intervention. The capture process triggers DMA transfers in high-performance applications, achieving measurement rates exceeding 10 MHz with sub-nanosecond resolution.

High-precision applications often employ time-to-digital converters (TDCs) integrated into modern microcontrollers, which use delay-line interpolation to achieve picosecond-level resolution. These circuits measure the phase difference between the event signal and the nearest clock edge, effectively subdividing the timer clock period.

3.2 Pulse Width Measurement

Pulse width measurement is a fundamental operation in microcontroller-based systems, enabling precise time-domain analysis of digital signals. The technique involves determining the duration of a pulse, defined as the time interval between its rising and falling edges (or vice versa). Microcontroller timers, configured in capture or input capture mode, are typically employed for this purpose.

Timer Capture Mode

When a timer is set to capture mode, it records the current counter value upon detecting a specified edge transition (rising or falling) on an input pin. The difference between two consecutive captures yields the pulse width. For instance, if the timer captures a value T₁ at a rising edge and T₂ at the subsequent falling edge, the pulse width PW is:

where t_clk is the timer clock period. High-resolution measurements require a fast timer clock or prescaler optimization.

Input Capture Units

Advanced microcontrollers feature dedicated input capture units (ICUs) that automate edge detection and timestamp recording. These units often include noise filters and programmable edge polarity selection. The ICU triggers an interrupt or DMA transfer upon capture, minimizing CPU overhead in real-time systems.

Measurement Resolution and Error Sources

The quantization error in pulse width measurement is bounded by:

Additional error sources include:

• Timer overflow: If the pulse width exceeds the timer's maximum count, overflow handling must be implemented.
• Signal jitter: High-frequency noise on the input signal causes edge detection uncertainty.
• Interrupt latency: Software-based capture methods suffer from variable response times.

Dual-Slope Measurement Technique

For improved accuracy in noisy environments, some systems employ a dual-slope approach where the timer measures both the high and low periods of a periodic signal. The pulse width PW and period T are derived from:

where N_high and N_low are the timer counts during the high and low phases, respectively. This method averages out high-frequency jitter.

Applications

• Duty cycle modulation: Closed-loop control of PWM-driven systems requires precise pulse width feedback.
• Time-of-flight sensors: Ultrasonic and optical rangefinders measure echo pulse widths to calculate distances.
• Digital communication: Pulse-width-encoded protocols (e.g., RC servo control, infrared remote signals) decode information in the time domain.

Hardware Considerations

Modern microcontrollers integrate specialized peripherals for pulse width measurement:

• STM32's Input Capture Mode with 16-bit resolution and 4x oversampling
• PIC microcontrollers' Enhanced Capture/Compare/PWM (ECCP) module
• ESP32's PCNT (Pulse Counter) peripheral with glitch filtering

3.3 External Triggering and Gate Control

Principles of External Triggering

External triggering allows a microcontroller timer to synchronize its counting operation with an external signal rather than relying solely on its internal clock. The trigger signal, typically a rising or falling edge, initiates or resets the timer's count sequence. This mechanism is crucial in applications requiring precise event synchronization, such as pulse-width modulation (PWM) generation, frequency measurement, or time-stamping external events.

The triggering condition is often configurable through control registers. For instance, the Timer Control Register (TCR) in many ARM Cortex-M microcontrollers provides bits to select between:

• Rising edge trigger - Timer starts/resets on low-to-high transition
• Falling edge trigger - Timer starts/resets on high-to-low transition
• Dual-edge trigger - Timer responds to both transitions

Where t_response is the delay between trigger and timer start, t_prop is the signal propagation delay through input synchronization circuits, and f_clk is the timer's clock frequency.

Gate Control Operation

Gate control extends external triggering by using an additional signal to enable or disable the counting process. When the gate signal is active (typically high), the timer increments on each clock cycle; when inactive, counting pauses regardless of clock activity. This creates a windowed counting operation useful for:

• Precise pulse width measurement
• Noise filtering by ignoring transitions during inactive gate periods
• Synchronized multi-timer operation in complex systems

The gate control logic can be modeled as:

Where FreeRun represents the timer's normal operation mode without external triggering.

Hardware Implementation

Modern microcontrollers implement external triggering and gate control through dedicated input capture pins with configurable digital filters. The signal path typically includes:

1. Input buffer with Schmitt trigger characteristics
2. Programmable digital noise filter (4-16 clock cycles)
3. Synchronization flip-flops (2-3 stages) to prevent metastability
4. Edge detection logic feeding into the timer control unit

The synchronization process introduces a deterministic latency that must be accounted for in precision applications:

Where N_sync is the number of synchronization stages (typically 2-3) and T_clk is the system clock period.

Practical Applications

In motor control systems, external triggering synchronizes PWM generation with rotor position sensors. The timer begins counting when a hall sensor triggers, ensuring precise commutation timing. Gate control prevents false triggering from electrical noise during inactive periods.

High-energy physics experiments use these features to timestamp particle detector events. A leading-edge trigger initiates the timer, while a trailing-edge gate signal defines the measurement window, rejecting afterpulses and noise.

Configuration Example

For an STM32 microcontroller, setting up external triggering with gate control involves:

// Configure Timer 2 for external trigger with gate control
TIM2->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_TS_0;  // Trigger on TI2FP2
TIM2->SMCR |= TIM_SMCR_SMS_2;                 // Gate mode
TIM2->CCMR1 |= TIM_CCMR1_CC2S_0;              // CC2 as input
TIM2->CCER |= TIM_CCER_CC2E;                  // Enable CC2
TIM2->CR1 |= TIM_CR1_CEN;                     // Enable timer
    

Timing Constraints

The maximum trigger frequency is limited by the timer's synchronization and processing logic:

Where N_filter is the configured filter length in clock cycles. For a 100 MHz timer with 3 synchronization stages and 4-cycle filtering, the maximum reliable trigger frequency is approximately 11.1 MHz.

Configuring Timers in Popular Microcontrollers (AVR, ARM, PIC)

AVR Timer Configuration

AVR microcontrollers, such as the ATmega328P, feature 8-bit and 16-bit timers with multiple operating modes. The Timer/Counter Control Registers (TCCRx) configure prescaler values, waveform generation modes, and interrupt enable bits. For a timer operating in CTC (Clear Timer on Compare Match) mode, the output compare register (OCRx) determines the period according to:

where f_clk is the system clock frequency and N is the prescaler value (1, 8, 64, 256, or 1024). To generate a 1 kHz signal with a 16 MHz clock and prescaler of 64:

// Configure Timer1 for CTC mode
TCCR1A = 0;
TCCR1B = (1 << WGM12) | (1 << CS11) | (1 << CS10); // Prescaler 64
OCR1A = 249; // 16000000 / (64 * 1000) - 1
TIMSK1 = (1 << OCIE1A); // Enable compare match interrupt
    

ARM Cortex-M Timers

ARM Cortex-M processors utilize the SysTick timer and General-Purpose Timers (TIMx). The SysTick timer, integrated into the NVIC, is commonly used for real-time operating systems. For a 16-bit TIMx timer in PWM mode, the auto-reload register (ARR) and prescaler (PSC) set the period:

To configure TIM2 for a 1 kHz PWM output with a 72 MHz clock:

// Enable TIM2 clock
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;

// Configure TIM2 for PWM mode 1
TIM2->PSC = 71; // Prescaler = 72 - 1
TIM2->ARR = 999; // Auto-reload value for 1 kHz
TIM2->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; // PWM mode 1
TIM2->CCER |= TIM_CCER_CC1E; // Enable output
TIM2->CR1 |= TIM_CR1_CEN; // Start timer
    

PIC Microcontroller Timers

PIC microcontrollers use the TMRx module with configurable prescalers and postscalers. The timer period is calculated as:

where T_osc is the oscillator period. For a PIC16F877A generating a 100 ms delay with a 4 MHz crystal and prescaler of 256:

// Configure Timer1
T1CON = 0x31; // Prescaler 1:8, Timer1 ON
TMR1H = 0x0B; // High byte for 3036 counts
TMR1L = 0xDC; // Low byte
TMR1IF = 0; // Clear interrupt flag
TMR1IE = 1; // Enable Timer1 interrupt
    

Practical Considerations

• Clock Synchronization: Asynchronous timer modes in AVR/PIC require careful handling to avoid metastability.
• Power Consumption: ARM timers can be gated using the RCC registers to minimize active power.
• Jitter Reduction: Using hardware capture/compare registers yields more precise timing than software polling.

4.2 Example: Generating Precise Delays

Fundamentals of Timer-Based Delay Generation

Precise timing is critical in embedded systems for tasks such as sensor polling, PWM generation, and communication protocols. Microcontroller timers, when configured in timer mode, increment their counter register at a fixed rate derived from the system clock or an external source. The delay duration T_delay is determined by:

where N is the number of clock cycles and T_clock is the period of the timer clock. For a 16-bit timer (e.g., Timer1 in ATmega328P), the maximum countable value is 65,535 (2¹⁶ - 1). Beyond this, overflow interrupts must be used to extend the delay range.

Configuring Timer Registers for Delay Calculation

The required timer count value N for a desired delay T_delay is calculated as:

where f_clock is the timer clock frequency. In practice, the prescaler value P divides the system clock f_CPU to produce f_clock:

Common prescaler values are 1, 8, 64, 256, and 1024. The optimal prescaler minimizes quantization error while avoiding timer overflow.

Practical Implementation on AVR Microcontrollers

The following steps outline delay generation using an AVR timer in CTC (Clear Timer on Compare Match) mode:

1. Select timer clock source and prescaler by configuring TCCR1B.
2. Calculate and set the compare match value OCR1A = N - 1.
3. Enable compare match interrupt by setting OCIE1A in TIMSK1.
4. Start the timer by writing to TCCR1B.
5. Implement the ISR to handle the elapsed delay.

// Generate 100ms delay on ATmega328P (16MHz clock)
#include <avr/io.h>
#include <avr/interrupt.h>

void timer1_init() {
    TCCR1A = 0;                     // Normal port operation
    TCCR1B = (1 << WGM12);          // CTC mode
    OCR1A = 15624;                  // 100ms at 16MHz/1024 prescaler
    TIMSK1 = (1 << OCIE1A);         // Enable compare match interrupt
    TCCR1B |= (1 << CS12) | (1 << CS10); // Start with 1024 prescaler
}

ISR(TIMER1_COMPA_vect) {
    // Delay complete - handle event here
}
    

Error Analysis and Optimization

The quantization error ε arises from integer truncation of N:

For sub-microsecond precision, consider:

• Using higher CPU frequencies (e.g., 48MHz instead of 16MHz)
• Selecting smaller prescaler values when possible
• Employing timer cascading for very long delays
• Using hardware capture/compare units for edge-aligned events

Advanced Techniques: Phase-Correct PWM for Fine Resolution

When sub-clock-cycle resolution is required, phase-correct PWM can generate delays with finer granularity. By varying the duty cycle at high frequency (e.g., 1MHz PWM), the effective delay resolution improves through averaging:

where T_PWM is the PWM period and 256 represents 8-bit resolution. This technique is particularly useful in laser ranging and time-of-flight applications where picosecond resolution may be required.

4.3 Example: Measuring Sensor Input Frequency

Fundamental Principles

Frequency measurement using microcontroller timers relies on capturing the number of signal edges (rising or falling) within a known time interval. For a periodic sensor signal with frequency f, the timer counts N edges over a gate time T_gate, yielding:

Timer peripherals in microcontrollers (e.g., STM32, AVR, or PIC) typically operate in input capture mode or counter mode, synchronized with an internal or external clock source.

Hardware Configuration

For a sensor outputting a square wave (e.g., an optical encoder or Hall-effect sensor):

• Connect the sensor output to a timer’s input capture pin (e.g., TI1 on STM32).
• Configure the timer in input capture mode with edge detection (rising/falling/both).
• Set the timer clock source (e.g., internal 16 MHz oscillator) and prescaler to achieve the desired resolution.

Mathematical Derivation

Assume a timer clock frequency f_clk and prescaler value P. The timer resolution Δt is:

For N captured edges over M timer ticks, the input frequency becomes:

Practical Implementation

An STM32 example using HAL libraries:

// Configure Timer 2 in input capture mode
TIM_HandleTypeDef htim2;
TIM_IC_InitTypeDef sConfigIC;

htim2.Instance = TIM2;
htim2.Init.Prescaler = 15; // Prescaler P=16 (15+1)
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
htim2.Init.Period = 0xFFFF; // Max timer period
HAL_TIM_IC_Init(&htim2);

sConfigIC.ICPolarity = TIM_ICPOLARITY_RISING;
sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
sConfigIC.ICFilter = 0;
HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_1);

// Start input capture
HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_1);

Error Analysis

Frequency measurement accuracy depends on:

• Timer resolution: Limited by f_clk and prescaler.
• Signal jitter: Noise or irregular edges introduce ±1 count uncertainty.
• Quantization error: Dominates at low frequencies, given by Δf = f_clk/(P⋅M).

Advanced Techniques

For high-precision measurements:

• Interrupt-driven timestamping: Record timer values at each edge to compute instantaneous frequency.
• Hardware averaging: Use multiple capture events to reduce quantization noise.
• Reciprocal counting: Measure the period between edges and invert to derive frequency, improving low-frequency accuracy.

5.1 Timer/Counter Chaining for Extended Range

Microcontroller timers and counters are typically constrained by their register bit-width, limiting their maximum count value. For instance, an 8-bit timer overflows at 255, while a 16-bit timer reaches 65,535. Many applications—such as long-duration event logging, high-precision frequency measurement, or motor control with extended pulse-width modulation (PWM) periods—require counting beyond these limits. Timer/counter chaining provides a solution by cascading multiple timers to achieve a combined effective bit-width.

Hardware and Software Chaining Methods

Chaining can be implemented in two primary ways:

• Hardware Chaining: The overflow signal of one timer triggers the increment of another. This method minimizes CPU overhead but requires specific microcontroller support (e.g., Timer1 overflow clocking Timer2 in AVR microcontrollers).
• Software Chaining: An interrupt service routine (ISR) increments a secondary counter upon overflow of the primary timer. This approach is more flexible but introduces latency due to ISR execution time.

Mathematical Derivation of Extended Range

When two n-bit timers are chained, the combined count range becomes:

For example, two 8-bit timers yield a 16-bit range (65,536), while two 16-bit timers produce a 32-bit range (4,294,967,296). The effective resolution R in seconds, given a clock frequency f_clk, is:

The maximum measurable time interval T_max becomes:

Practical Implementation Considerations

Chaining introduces trade-offs between resolution and latency:

• Synchronization Errors: In software chaining, ISR latency causes a slight undercounting. The error E is bounded by the ISR response time t_ISR:
  $$ E \leq t_{ISR} \times f_{clk} $$
• Power Consumption: Hardware chaining keeps peripherals active, while software chaining allows sleep modes between overflows.

Case Study: AVR Timer Chaining

On ATmega microcontrollers, Timer1 (16-bit) can be chained with Timer2 (8-bit) by configuring Timer1’s overflow to trigger Timer2’s clock. The following assembly snippet demonstrates initialization:

; Configure Timer1 for normal mode, overflow interrupt
ldi r16, (1<

5.2 Low-Power Timer Operation

5.3 Debugging Common Timer/Counter Issues

6.1 Recommended Books and Datasheets

6.2 Online Resources and Tutorials

6.3 Community Forums and Support