AD2S80A AD2S81A AD2S82A RDC monolithic integrated circuit

Posted on Mar 28, 2007

AD2S80A RDC tracking monolithic integrated circuit is ANALOG DE Vices latest generation RDC. It can be used to Synchro, resolver, inductive synchronizer digital conversion. It

AD2S80A AD2S81A AD2S82A RDC monolithic integrated circuit
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is the advanced CMOS logic and bipolar high accuracy linear circuits combined to BiMOS l production process in the same chip. AD2S80A resolution and dynamic performance and AD2S82A can be user selected, choose the sub resolution has 10,12] 4,16bit. AD2S81A is fixed resolution (12hit) of the RDC. Because they will resolver signal convertors is a natural binary number is adopt a ratiometric tracking method, only output digital angle and the sine and cosine signals input ratio of relevant, irrespective of their absolute size, it has a high noise suppression capability, reduced due to the distance from the rotary transformer via a converter error caused by long-term difference. 16 data output lines have three-state output data latch function, use BYTE SELECT pin control, etc., can be transmitted to the data bus 8bit or 16bit. Can also output analog signal proportional to the speed (VELOCITY O/P), used in place of speed made the motor. The reference voltage frequency range 50Hz-20kHz. Recommended operating conditions: Supply voltage ( V,) 10% of persons with disabilities 12V logic supply voltage (vl) + 5v 10% rms voltage analog input signal (sin, cos) 2V disabilities 10% reference voltage 1-8V input eight signals and the reference voltage distortion 10% (max) between the input signal and the reference voltage phase shift 10. (max) 1. AD2S80A RDC 8 12 shows the internal block diagram of AD2S80A and external connections. After connection Figure, AD2S80A on the run in the previous section I servo tracking RDC ring. Digital output to select the tracking speed automatically track the input channel number. Since the conversion ratio of the input SIN and only cos signals are, therefore input signal amplitude and frequency allow q within a certain range. Since the phase sensitive detector demodulator prisoners in, the reference voltage quadrature component has a high rejection. Its digital output resolution of 10, 12] 4,16bit by SC1 and SC2 output

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