Switched-Capacitor Circuits

1. Basic Principles of Charge Transfer

Basic Principles of Charge Transfer

The fundamental operation of switched-capacitor circuits relies on the controlled transfer of charge between capacitors via active switches. Unlike continuous-time circuits, charge transfer occurs in discrete time intervals, governed by clock signals that toggle the switches.

Charge Redistribution Mechanism

Consider two capacitors, C1 and C2, initially charged to voltages V1 and V2, respectively. When connected through a switch, charge redistributes until equilibrium is reached. The final voltage Vf across both capacitors is derived from charge conservation:

$$ C_1 V_1 + C_2 V_2 = (C_1 + C_2) V_f $$

Solving for Vf:

$$ V_f = \frac{C_1 V_1 + C_2 V_2}{C_1 + C_2} $$

This principle forms the basis for charge-sharing operations in switched-capacitor filters, data converters, and voltage regulators.

Non-Ideal Effects in Charge Transfer

Practical implementations must account for:

Equivalent Resistance Concept

A switched-capacitor network can emulate a resistor by toggling a capacitor between two nodes at frequency fsw. The average current flow is:

$$ I_{avg} = C \frac{\Delta V}{T_{sw}} = C f_{sw} \Delta V $$

yielding an equivalent resistance:

$$ R_{eq} = \frac{\Delta V}{I_{avg}} = \frac{1}{C f_{sw}} $$

This enables compact RC filter implementations in IC designs, where precise resistor values are difficult to fabricate.

Parasitic Capacitance Effects

Bottom-plate parasitic capacitance (Cp) to substrate alters charge transfer efficiency. For a capacitor C sharing charge through a switch:

$$ V_f = \frac{C}{C + C_p} V_{initial} $$

Modern layouts use top-plate sampling or shield layers to minimize this effect. In differential circuits, even-order parasitics cancel out, preserving linearity.

C₁ C₂ SW
Charge Redistribution Between Capacitors A schematic diagram showing two capacitors (C₁ and C₂) connected via a switch (SW), illustrating charge redistribution with labeled initial voltages (V₁, V₂) and final voltage (V_f). C₁ V₁ C₂ V₂ SW V_f (after redistribution)
Diagram Description: The diagram would physically show two capacitors connected via a switch, illustrating the charge redistribution mechanism described in the text.

1.2 Capacitor Switching Techniques

Switched-capacitor circuits rely on precise charge transfer between capacitors via controlled switching. The two dominant methodologies are voltage-based and charge-based switching, each offering distinct tradeoffs in precision, speed, and power consumption.

Voltage-Driven Switching

In voltage-mode operation, capacitors are alternately connected between voltage sources and ground through MOSFET switches. The charge transfer follows:

$$ Q = C \cdot \Delta V $$

where ΔV is the potential difference between switching phases. Non-idealities manifest through:

Phase 1 Phase 2

Charge Redistribution Technique

This method employs complementary switching phases to transfer discrete charge packets:

$$ \Delta Q = C \left( V_{ref}^+ - V_{ref}^- \right) $$

Critical considerations include:

Bottom-Plate Switching

A refined approach that minimizes charge injection by keeping the top plate at virtual ground while switching occurs only on the bottom plate. The transfer function becomes:

$$ V_{out} = \frac{C_1}{C_2} \cdot V_{in} \cdot f_{sw} \cdot T_{clk} $$

where fsw is the switching frequency and Tclk the clock period. This technique is prevalent in:

Advanced Techniques

Modern implementations employ:

$$ SNR = 10 \log \left( \frac{C \cdot V_{FS}^2}{8kT} \right) $$

where VFS is the full-scale voltage. Practical implementations in 65nm CMOS achieve >90dB SNR at 100MS/s with capacitor matching below 0.01%.

Capacitor Switching Phases and Charge Transfer Schematic diagram showing two-phase capacitor switching with MOSFET switches, voltage sources, and timing diagram inset illustrating charge transfer between phases. Phase Φ1 Vref+ Vref- S1 S2 C Q = CΔV Phase Φ2 Vout S3 Clock Signals Φ1 Φ2 Charge injection Charge injection
Diagram Description: The section describes capacitor switching phases and charge transfer mechanisms that benefit from visual representation of switching states and signal paths.

1.3 Charge Conservation and Voltage Scaling

Fundamental Principle of Charge Conservation

In switched-capacitor circuits, charge conservation governs the redistribution of charge between capacitors during switching operations. When two capacitors C1 and C2 with initial voltages V1 and V2 are connected, the total charge remains constant. The final equilibrium voltage Vf can be derived from:

$$ Q_{total} = C_1V_1 + C_2V_2 = (C_1 + C_2)V_f $$

Solving for Vf:

$$ V_f = \frac{C_1V_1 + C_2V_2}{C_1 + C_2} $$

Voltage Scaling in Capacitive Networks

When charge is transferred between unequal capacitors, voltage scaling occurs. Consider a charge transfer from C1 to C2 where C2 = kC1:

$$ \Delta V = V_1 - V_f = V_1 - \frac{C_1V_1}{C_1 + kC_1} = V_1\left(1 - \frac{1}{1 + k}\right) $$

This demonstrates how the voltage scaling factor depends on the capacitor ratio k. For k = 1 (equal capacitors), the voltage divides equally, while for k ≫ 1, the voltage change becomes negligible.

Practical Implementation in SC Circuits

Switched-capacitor voltage multipliers exploit this principle through phased switching:

  1. Phase 1 (Charging): C1 charges to Vin
  2. Phase 2 (Transfer): C1 connects in series/parallel with C2
  3. Result: Output voltage scales by C1/(C1 + C2)

This mechanism forms the basis for charge pumps and switched-capacitor DC-DC converters, where capacitor ratios precisely control voltage conversion ratios.

Non-Ideal Effects

Practical implementations must account for:

The modified charge conservation equation including parasitic capacitance Cp becomes:

$$ V_f' = \frac{C_1V_1 + C_2V_2}{C_1 + C_2 + C_p} $$

Modern IC designs minimize these effects through symmetrical layout techniques and bootstrap switching.

2. Design and Analysis of SC Filters

2.1 Design and Analysis of SC Filters

Switched-capacitor (SC) filters leverage the principle of charge transfer between capacitors via switches to emulate resistor behavior, enabling precise and tunable frequency responses. The core mechanism relies on the equivalence between a switched capacitor and an equivalent resistance, given by:

$$ R_{eq} = \frac{1}{f_s C} $$

where fs is the switching frequency and C is the capacitance. This equivalence allows SC circuits to replace resistors in traditional active-RC filters, offering advantages in monolithic integration and programmability.

Transfer Function Derivation

The analysis of SC filters typically employs the z-domain due to their discrete-time operation. Consider a first-order SC integrator, the building block of higher-order filters. Its charge transfer equation during phase φ1 (sampling) and φ2 (integration) yields:

$$ V_{out}(z) = \frac{C_1}{C_2} \frac{z^{-1}}{1 - z^{-1}} V_{in}(z) $$

This matches the z-domain representation of an analog integrator with a gain factor C1/C2. For a second-order SC filter (e.g., biquad), the transfer function generalizes to:

$$ H(z) = \frac{a_0 + a_1 z^{-1} + a_2 z^{-2}}{1 + b_1 z^{-1} + b_2 z^{-2}} $$

where coefficients ai and bi are determined by capacitor ratios and switching timing.

Parasitic Sensitivity and Non-Ideal Effects

Practical SC filters face parasitic capacitances (Cp) from switches and nodes, introducing errors in the charge transfer. The modified equivalent resistance becomes:

$$ R_{eq} = \frac{1}{f_s (C + C_p)} $$

Clock feedthrough and charge injection from MOS switches further distort the output. These effects are mitigated through:

Design Methodology

The synthesis of SC filters follows these steps:

  1. Select filter type (Butterworth, Chebyshev, etc.) based on passband ripple and roll-off requirements.
  2. Bilinear transform the analog prototype to z-domain:
$$ s = \frac{2}{T} \frac{1 - z^{-1}}{1 + z^{-1}} $$
  1. Map capacitor ratios to z-domain coefficients. For example, a biquad section’s pole frequency (ω0) and Q-factor are set by:
$$ \omega_0 \approx f_s \sqrt{\frac{C_1}{C_3}}, \quad Q \approx \sqrt{\frac{C_1 C_3}{C_2^2}} $$
  1. Simulate with non-idealities (e.g., finite op-amp gain, settling time) using tools like SPICE or MATLAB.

Applications and Case Study

SC filters dominate voice-band processing in telecommunications (e.g., anti-aliasing in PCM codecs) and sensor interfaces (e.g., delta-sigma ADCs). A notable implementation is the MF10 universal SC filter IC, configurable as low-pass, high-pass, or band-pass with external clock tuning.

2.2 Bilinear and LDI Transformations

The bilinear transformation and lossless discrete integrator (LDI) transformation are two fundamental techniques for converting continuous-time filters into their switched-capacitor equivalents. These mappings preserve critical filter characteristics while adapting them for discrete-time operation.

Bilinear Transformation

The bilinear transformation provides a one-to-one mapping between the continuous-time Laplace domain (s-domain) and the discrete-time z-domain. It is defined by:

$$ s = \frac{2}{T} \frac{1 - z^{-1}}{1 + z^{-1}} $$

where T is the sampling period. This transformation:

$$ \omega_a = \frac{2}{T} \tan\left(\frac{\omega_d T}{2}\right) $$

where ωa is the analog frequency and ωd is the discrete frequency. For narrow bandwidths relative to the sampling frequency, this warping becomes negligible.

LDI Transformation

The lossless discrete integrator (LDI) transformation offers an alternative mapping particularly suited for ladder filter implementations:

$$ s = \frac{1}{T} (z^{1/2} - z^{-1/2}) $$

Key properties of the LDI approach include:

Implementation Considerations

When implementing these transformations in switched-capacitor circuits:

For a second-order section with cutoff frequency ω0 and quality factor Q, the bilinear-transformed difference equation becomes:

$$ y[n] = \frac{b_0x[n] + b_1x[n-1] + b_2x[n-2] - a_1y[n-1] - a_2y[n-2]}{a_0} $$

where the coefficients are derived from the analog prototype through algebraic substitution of the transformation.

Comparison of Approaches

The choice between transformations depends on application requirements:

Characteristic Bilinear LDI
Frequency warping Significant Minimal
Phase response Nonlinear More linear
Implementation complexity Lower Higher
Dynamic range Good Excellent

In practice, bilinear transformation is preferred for general-purpose filters, while LDI finds use in high-performance applications like precision anti-aliasing filters where phase linearity is critical.

Bilinear vs LDI Transformations in s-plane and z-plane Comparison of frequency warping effects between bilinear and LDI transformations, showing their mapping between s-plane and z-plane with analog and discrete frequency axes. Bilinear vs LDI Transformations in s-plane and z-plane Bilinear Transformation s-plane z-plane tan(ω_d T/2) ω_a ω_d Nyquist frequency LDI Transformation s-plane z-plane ω_d T/2 ω_a ω_d Nyquist frequency Stability Region (Bilinear): Left s-plane → Inside unit circle Stability Region (LDI): Left s-plane → Inside unit circle Bilinear Warping LDI Warping
Diagram Description: The diagram would show the frequency warping effect comparison between bilinear and LDI transformations, and their mapping between s-plane and z-plane.

2.3 Practical Considerations in Filter Implementation

Non-Ideal Op-Amp Effects

The finite gain-bandwidth product (GBW) of operational amplifiers introduces errors in the transfer function of switched-capacitor filters. For an integrator stage, the ideal transfer function:

$$ H_{ideal}(z) = \frac{C_1}{C_2}\frac{z^{-1}}{1 - z^{-1}} $$

becomes modified by the finite op-amp gain A and bandwidth:

$$ H_{actual}(z) \approx \frac{C_1}{C_2}\frac{z^{-1}}{1 - z^{-1}(1 + \frac{1}{A} + \frac{1}{\beta A})} $$

where β is the feedback factor. For typical CMOS op-amps with GBW = 10 MHz, this creates noticeable deviation above 100 kHz.

Capacitor Ratio Matching

Modern CMOS processes achieve capacitor matching of 0.1% or better when using:

The relative error ΔC/C between matched capacitors follows a normal distribution:

$$ \frac{\Delta C}{C} \sim \mathcal{N}(0, \sigma^2) $$

where σ ≈ 0.05% for carefully laid out 100 fF capacitors in 65nm CMOS.

Clock Feedthrough and Charge Injection

MOSFET switches introduce errors through two mechanisms:

  1. Clock feedthrough: Capacitive coupling of clock edges via Cgd
  2. Charge injection: Channel charge redistribution when switches turn off

The total error voltage at the sampling instant can be modeled as:

$$ V_{error} = \frac{C_{ov}}{C_s}V_{clk} + \frac{WLC_{ox}(V_{clk}-V_{th})}{2C_s} $$

where Cov is the overlap capacitance, Cs the sampling capacitor, and W/L the switch dimensions. Differential architectures cancel even-order terms of this error.

kT/C Noise

The fundamental noise floor of a switched-capacitor circuit is set by thermal noise sampling:

$$ \overline{v_n^2} = \frac{kT}{C_s} $$

For a 1 pF sampling capacitor at 300K, this equals 64 μVrms. Cascading multiple stages increases the total noise power by the squared sum of individual stage noise contributions.

Parasitic Insensitivity

A key advantage of switched-capacitor circuits is their inherent rejection of certain parasitics. The transfer function remains unaffected by:

This occurs because these parasitics are either switched between low-impedance nodes or appear at virtual grounds during critical phases.

Anti-Aliasing Requirements

Despite operating in discrete time, switched-capacitor filters require continuous-time anti-aliasing filters (AAF) at their inputs. The AAF corner frequency must satisfy:

$$ f_{AAF} \leq \frac{f_s}{2} - f_{signal}^{max} $$

where fs is the sampling frequency. A 2nd-order active RC filter with Q=0.707 typically suffices for moderate dynamic range applications.

3. Operational Amplifiers in SC Circuits

Operational Amplifiers in SC Circuits

Operational amplifiers (op-amps) are fundamental building blocks in switched-capacitor (SC) circuits, providing high gain, precise charge transfer, and low output impedance. Their behavior in SC networks differs from continuous-time counterparts due to discrete-time charge redistribution and settling dynamics.

Op-Amp Requirements in SC Circuits

SC circuits impose specific performance constraints on op-amps:

The settling time constant Ï„ is dominated by the op-amp's GBW when driving capacitive loads:

$$ \tau = \frac{1}{2\pi \cdot \text{GBW}} \cdot \left(1 + \frac{C_L}{C_C}\right) $$

where CL is the load capacitance and CC is the compensation capacitance.

Charge Transfer Analysis

During φ1 (sampling phase), capacitor C1 charges to Vin. During φ2 (transfer phase), charge redistributes to C2 through the virtual ground:

$$ Q_{\text{transfer}} = C_1(V_{\text{in}} - V^-) = -C_2V_{\text{out}} $$

With ideal op-amp assumptions (V- → 0, infinite gain), the transfer function becomes:

$$ \frac{V_{\text{out}}}{V_{\text{in}}} = -\frac{C_1}{C_2} $$

Non-Ideal Effects

Finite Op-Amp Gain

With finite gain A0, the transfer function modifies to:

$$ \frac{V_{\text{out}}}{V_{\text{in}}} = -\frac{C_1}{C_2} \left( \frac{1}{1 + \frac{1 + C_1/C_2}{A_0}} \right) $$

For 12-bit accuracy, A0 typically needs to exceed 80 dB when C1/C2 = 1.

Thermal Noise

The total output-referred noise power in an SC integrator is:

$$ \overline{v_n^2} = \frac{kT}{C_s} \left(1 + \frac{C_p}{C_s}\right) + \frac{4kT}{C_f}(1 + \gamma)g_mR_{\text{out}}} $$

where Cp is parasitic capacitance, γ is the op-amp's noise factor, and gm is the input transconductance.

Advanced Compensation Techniques

Modern SC circuits employ specialized compensation methods:

The stability condition for a two-stage op-amp in SC circuits requires:

$$ \text{Phase Margin} > 60^\circ \quad \text{and} \quad \text{GBW} < \frac{0.2}{T_{\text{sample}}}} $$
C1 C2 Vout Vin φ1 φ2
SC Integrator with Op-Amp and Clock Phases Schematic of a switched-capacitor integrator showing the circuit topology during both clock phases (φ₁ and φ₂), including op-amp, capacitors C₁/C₂, switches, input Vin, output Vout, and virtual ground. V⁻ Vin C₁ φ₁ φ₂ C₂ φ₁ φ₂ Vout φ₁ Phase: C₁ charges from Vin, C₂ discharges to output φ₂ Phase: C₁ discharges to virtual ground, C₂ charges
Diagram Description: The section describes charge transfer phases (φ₁/φ₂) and circuit topology involving capacitors C₁/C₂ with op-amp interactions, which are inherently spatial relationships.

3.2 Gain and Bandwidth Considerations

Gain in Switched-Capacitor Circuits

The voltage gain of a switched-capacitor (SC) circuit is primarily determined by the ratio of capacitances and the switching frequency. For a basic SC amplifier, the gain Av is given by:

$$ A_v = -\frac{C_1}{C_2} $$

where C1 is the input sampling capacitor and C2 is the feedback capacitor. This relationship arises because charge redistribution between the capacitors during each switching phase enforces a voltage ratio proportional to their capacitance values.

In practice, parasitic capacitances and finite op-amp gain introduce deviations from the ideal gain. The modified gain expression, accounting for finite op-amp gain A0, becomes:

$$ A_v \approx -\frac{C_1}{C_2} \left(1 - \frac{1 + \frac{C_1}{C_2}}{A_0}\right) $$

This correction term becomes significant when A0 is not substantially larger than the designed gain.

Bandwidth Limitations

The bandwidth of an SC circuit is constrained by two primary factors:

The effective small-signal bandwidth fBW of an SC integrator, for instance, can be approximated by:

$$ f_{BW} = \frac{f_{sw}}{2\pi} \cdot \frac{g_m}{C_2} $$

where gm is the transconductance of the op-amp. This highlights the trade-off between speed and power consumption—higher bandwidth requires either increased gm (and thus higher bias current) or reduced C2 (which increases noise).

Trade-offs in Gain-Bandwidth Product

Unlike continuous-time amplifiers, SC circuits do not have a fixed gain-bandwidth product (GBW). Instead, their dynamic performance is dictated by:

A practical design rule ensures the op-amp's GBW satisfies:

$$ \text{GBW} \gg \frac{f_{sw} \cdot A_v}{2\pi} $$

This guarantees that the amplifier settles adequately within each clock phase, preventing gain error and phase distortion.

Noise Considerations

Thermal noise in SC circuits manifests as kT/C noise, where the total integrated noise power is:

$$ \overline{v_n^2} = \frac{kT}{C_{eq}} $$

Here, Ceq represents the equivalent capacitance seen at the output node. For a switched-capacitor integrator, this is typically dominated by the feedback capacitor C2. Increasing C2 reduces noise but degrades bandwidth, illustrating another key trade-off.

Practical Design Implications

In high-speed SC circuits (e.g., data converters), designers must:

For example, in a pipelined ADC, interstage gain errors directly impact linearity. Mismatch between C1 and C2 due to process variations can be mitigated using common-centroid layout techniques.

Switched-Capacitor Amplifier Charge Redistribution A schematic diagram of a switched-capacitor amplifier showing charge redistribution between input capacitor C1 and feedback capacitor C2 during two clock phases Φ1 and Φ2, with an op-amp and switches. - + Vout C1 C2 Φ1 Φ1 Φ2 Vin Charge flow Φ1 Charge flow Φ2 Φ1 Φ2 Clock Phases
Diagram Description: The section involves charge redistribution between capacitors and settling behavior of op-amps, which are highly visual concepts.

Noise and Offset Compensation Techniques

Noise Sources in Switched-Capacitor Circuits

Switched-capacitor circuits are susceptible to several noise sources, including thermal noise, flicker noise, and charge injection from switches. Thermal noise, arising from resistive elements such as MOSFET switches, is given by:

$$ \overline{v_n^2} = 4kTR_{on} \Delta f $$

where k is Boltzmann's constant, T is temperature, Ron is the switch on-resistance, and Δf is the bandwidth. Flicker noise, dominant at low frequencies, follows a 1/f characteristic and is particularly problematic in CMOS implementations.

kT/C Noise Limit

The fundamental noise floor in switched-capacitor circuits is determined by the kT/C noise, representing the thermal energy stored on a capacitor. When a capacitor is charged through a switch, the resulting noise voltage is:

$$ \overline{v_n^2} = \frac{kT}{C} $$

This imposes a critical trade-off between noise performance and capacitor size, as larger capacitors reduce noise but increase area and power consumption.

Correlated Double Sampling (CDS)

Correlated double sampling is a widely used technique to mitigate offset and low-frequency noise. The method involves sampling the noise/offset in one phase and subtracting it from the signal in the subsequent phase. The effective offset Vos after CDS is reduced to:

$$ V_{os,eff} = V_{os} \left(1 - e^{-\frac{T}{\tau}}\right) $$

where T is the sampling period and Ï„ is the time constant of the circuit. CDS is particularly effective in amplifiers and integrators where DC offsets would otherwise accumulate.

Chopper Stabilization

Chopper stabilization modulates the input signal to a higher frequency where flicker noise is negligible, then demodulates it back to baseband after amplification. The modulated signal bypasses the 1/f noise region, resulting in a noise spectrum dominated by white noise. The effectiveness of chopping depends on the chopping frequency fchop being well above the flicker noise corner frequency.

Autozeroing Techniques

Autozeroing periodically samples and stores the offset voltage on a capacitor, then subtracts it from the input signal. The residual offset after autozeroing is limited by charge injection and clock feedthrough. The settling behavior follows:

$$ V_{residual} = V_{offset} \frac{C_{par}}{C_{az} + C_{par}} $$

where Caz is the autozero capacitor and Cpar represents parasitic capacitances. Modern implementations often combine autozeroing with chopping for optimal noise performance.

Practical Considerations in Compensation

In high-precision applications, the choice between CDS, chopping, and autozeroing involves trade-offs in power, speed, and circuit complexity. For example, chopper stabilization requires careful design of the modulator/demodulator to avoid signal distortion, while CDS demands precise timing control to ensure proper cancellation. Recent advances in dynamic element matching further improve performance by averaging out capacitor mismatches.

CDS Noise Cancellation Sampling Holding

4. Data Converters (ADCs and DACs)

Switched-Capacitor Data Converters (ADCs and DACs)

Fundamentals of Switched-Capacitor ADCs

Switched-capacitor analog-to-digital converters (ADCs) leverage charge redistribution to achieve high precision without relying on passive component matching. The core principle involves sampling an input voltage onto a capacitor network and then redistributing charge through a series of switching operations controlled by a clock signal. The charge transfer process is governed by:

$$ Q = C \cdot V $$

where Q is the stored charge, C is the capacitance, and V is the sampled voltage. By toggling switches at a frequency fclk, the circuit emulates a resistor with an equivalent resistance:

$$ R_{eq} = \frac{1}{f_{clk} \cdot C $$

Successive Approximation Register (SAR) ADC Architecture

A common switched-capacitor implementation is the SAR ADC, which uses a binary search algorithm. The process involves:

SAR Logic

Charge-Redistribution DAC Operation

In switched-capacitor digital-to-analog converters (DACs), a binary-weighted capacitor array generates an analog output. The output voltage Vout for an N-bit DAC is:

$$ V_{out} = V_{ref} \cdot \frac{\sum_{k=0}^{N-1} b_k \cdot 2^k}{2^N} $$

where bk are the digital input bits. Capacitor mismatch and charge injection are dominant error sources, requiring calibration techniques like dynamic element matching.

Noise and Performance Limitations

Key performance metrics include:

Advanced Techniques

Modern designs employ:

SAR ADC Charge Redistribution Phases A timed block diagram showing the sampling, redistribution, and conversion phases of a SAR ADC with capacitor array, switches, comparator, and SAR logic. Sampling (φ1) Redistribution (φ2) Conversion t0 t1 t2 t3 C 2C 4C ... 2ⁿC φ1 φ1 φ1 φ1 φ1 φ2 Comparator SAR Logic DAC Feedback VIN GND
Diagram Description: The section describes a multi-phase charge redistribution process in SAR ADCs and capacitor arrays, which involves spatial switching sequences and voltage transitions.

Power Management and DC-DC Conversion

Fundamentals of Switched-Capacitor DC-DC Converters

Switched-capacitor (SC) DC-DC converters leverage charge transfer between capacitors via controlled switches to achieve voltage conversion without magnetic components. The basic operation relies on alternating between two phases: charging and discharging. During the charging phase, capacitors are connected to the input voltage, storing energy. In the discharging phase, they are reconfigured to deliver energy to the output.

The voltage conversion ratio is determined by the capacitor network topology. For a simple 2:1 step-down converter, the output voltage Vout is ideally half the input voltage Vin:

$$ V_{out} = \frac{1}{2} V_{in} $$

Charge Pump Architectures

Common SC converter topologies include:

The equivalent output resistance Rout of an SC converter, which determines its efficiency under load, is given by:

$$ R_{out} = \frac{1}{f_{sw} C_{eq}} $$

where fsw is the switching frequency and Ceq is the equivalent capacitance of the network.

Efficiency Considerations

The theoretical efficiency η of an ideal SC converter is 100%, but practical implementations face losses due to:

The total power loss Ploss can be modeled as:

$$ P_{loss} = I_{out}^2 R_{out} + f_{sw} C_{par} V_{in}^2 $$

where Cpar represents the total parasitic capacitance.

Advanced Techniques

Soft-Charging

Soft-charging techniques reduce losses by minimizing voltage differences during capacitor reconfiguration. This is achieved through intermediate voltage steps or resonant transitions.

Multiphase Interleaving

Using multiple switched-capacitor stages operating out of phase reduces output voltage ripple and improves transient response. The ripple voltage ΔV for an N-phase interleaved converter is:

$$ \Delta V = \frac{I_{out}}{N f_{sw} C} $$

Practical Applications

Switched-capacitor DC-DC converters are widely used in:

Modern implementations achieve >90% efficiency at power densities exceeding 1W/mm² in advanced CMOS processes.

Switched-Capacitor Topologies and Phase Operation Side-by-side comparison of series-parallel, Fibonacci, and Dickson switched-capacitor configurations with labeled charging and discharging phases. Series-Parallel φ1 (Charging) Vin Vout C1 φ2 (Discharging) C1 Vout Fibonacci φ1 (Charging) C1 C2 Vin φ2 (Discharging) Vout Dickson φ1 (Charging) C1 C2 Vin φ2 (Discharging) Vout Phase Timing (φ1 → φ2) Closed switch (active phase) Open switch (inactive phase) Capacitor
Diagram Description: The section describes multiple switched-capacitor topologies (series-parallel, Fibonacci, Dickson) and their phase-based operation, which are inherently spatial concepts.

4.3 Sensor Interface Circuits

Switched-capacitor (SC) techniques are widely employed in sensor interfacing due to their ability to perform precision analog signal conditioning without relying on passive component matching. These circuits excel in applications requiring high resolution, low noise, and compatibility with digital CMOS processes.

Charge-Balancing Sensor Readout

A fundamental SC sensor interface employs charge-balancing to convert a sensor's impedance variation into a digital-readable voltage. Consider a capacitive sensor CS whose value changes with the measured quantity (pressure, acceleration, etc.). The basic operation involves:

$$ Q_{total} = C_S V_{ref} - C_F V_{out} = 0 $$

where CF is a fixed feedback capacitor. Solving for the output voltage:

$$ V_{out} = \frac{C_S}{C_F} V_{ref} $$

This ratiometric relationship makes the circuit insensitive to clock frequency variations. The kT/C noise limit of such interfaces is given by:

$$ \overline{v_n^2} = \frac{kT}{C_S} $$

Correlated Double Sampling (CDS) Technique

To mitigate low-frequency noise and offset errors, SC sensor interfaces often implement CDS. The technique works by sampling the noise/offset in one phase and subtracting it from the signal in the subsequent phase:

  1. Phase φ1: Sample noise + offset on auxiliary capacitor CA
  2. Phase φ2: Acquire signal + noise on CS
  3. Output stage performs Vout = (Vsignal + Vnoise) - Vnoise

This typically improves the effective resolution by 3-4 bits compared to single-sampling approaches.

Bridge Sensor Interfaces

For resistive sensors in Wheatstone bridge configurations, SC circuits provide an elegant solution for offset cancellation and amplification. A typical implementation uses:

The output voltage for a bridge with resistance variation ΔR becomes:

$$ V_{out} = \frac{C_1}{C_2} \left( \frac{\Delta R}{4R_0} \right) V_{exc} $$

where Vexc is the bridge excitation voltage and R0 the nominal resistance.

Delta-Sigma Modulator Interfaces

High-resolution sensor applications often employ SC-based ΔΣ modulators. The first-order modulator shown below provides inherent noise shaping:

SC ΔΣ Modulator

The modulator's oversampling ratio (OSR) and order determine its effective number of bits (ENOB):

$$ ENOB = \frac{10 \log_{10}(OSR^{2N+1}) - 12.9}{6.02} $$

where N is the modulator order. Practical implementations achieve 16-24 bit resolution for bandwidths below 1 kHz.

Micro-Power Design Techniques

For energy-constrained sensor nodes, several SC techniques minimize power:

Technique Power Reduction Trade-off
Subthreshold operation 10-100× Reduced bandwidth
Time-interleaved sampling 3-5× Increased area
Charge recycling 2-3× Complex control

State-of-the-art implementations achieve sub-μW power consumption for biomedical sensors and IoT devices while maintaining 12-16 bit resolution.

5. Parasitic Insensitivity Techniques

5.1 Parasitic Insensitivity Techniques

Fundamental Challenge of Parasitic Capacitances

Switched-capacitor circuits rely on precise charge transfer between capacitors, but parasitic capacitances (Cp)—stemming from device junctions, interconnects, and fringing fields—introduce nonlinearity and signal attenuation. For a basic switched-capacitor integrator, the effective integration capacitance becomes Ceff = C + Cp, where C is the intended capacitance. This alters the transfer function:

$$ H(z) = \frac{C}{C + C_p} \cdot \frac{z^{-1}}{1 - z^{-1}} $$

Parasitics degrade gain accuracy and linearity, particularly in high-resolution ADCs or precision filters. Mitigation requires topological and timing techniques.

Topological Solutions

Bottom-Plate Switching

Parasitic capacitances to ground (Cp1, Cp2) dominate in MOS switches. By driving the bottom plate (rather than the top plate) with the clock signal, charge injection couples to ground instead of the signal path. This is achieved by:

Fully Differential Architectures

Differential operation cancels even-order parasitics. For a differential pair with parasitics Cp+ and Cp-, the output voltage becomes:

$$ V_{out} = \left( \frac{C}{C + C_{p+}} - \frac{C}{C + C_{p-}} \right) V_{in} \approx \frac{C \Delta C_p}{(C + C_p)^2} V_{in} $$

Mismatches (ΔCp) introduce second-order errors, but these are negligible for symmetric layouts.

Clock Phase Optimization

Parasitic-sensitive circuits often use two-phase non-overlapping clocks (Ï•1, Ï•2). Adding a third phase (Ï•reset) discharges parasitics before integration. The timing sequence:

  1. Reset phase: Short parasitics to a known voltage (e.g., VCM)
  2. Sampling phase: Charge transfer via Ï•1
  3. Integration phase: Charge redistribution via Ï•2

Advanced Techniques

Correlated Double Sampling (CDS)

CDS measures and subtracts parasitic-induced offset during a reset phase. For a capacitive amplifier:

$$ V_{out} = \left( 1 + \frac{C_p}{C_f} \right) (V_{in} - V_{offset}) $$

By sampling Voffset during reset and subtracting it from the active phase, Cp effects are nulled.

Flying Capacitor Buffering

Inserting a buffer between switched capacitors isolates parasitics. The buffer’s low output impedance prevents charge sharing with downstream parasitics, preserving signal integrity.

Practical Considerations

In 65nm CMOS processes, bottom-plate switching reduces parasitic sensitivity by 40dB compared to top-plate switching. However, clock feedthrough increases with frequency—requiring trade-offs in GHz-range designs. For biomedical applications (e.g., EEG readouts), CDS achieves <100nV residual offset.

Bottom-Plate Switching & Clock Phasing A schematic of bottom-plate switching with substrate connection (left) and a timing diagram of three-phase clock signals (right). C Cp1 Cp2 Ï•1 Ï•2 VCM Ground Signal Path Substrate Ï•1 Ï•2 Ï•reset Reset Sampling Integration Time Bottom-Plate Switching & Clock Phasing
Diagram Description: The section describes spatial techniques like bottom-plate switching and clock phase sequencing, which are inherently visual and require showing capacitor/switch arrangements and timing relationships.

5.2 Clock Feedthrough and Charge Injection

In switched-capacitor circuits, two dominant non-ideal effects arise from MOS switch operation: clock feedthrough and charge injection. These phenomena introduce errors that degrade precision in sampled-data systems, particularly affecting analog-to-digital converters, filters, and correlated double sampling circuits.

Physical Mechanisms

When a MOS transistor switch turns off, two concurrent processes occur:

The gate-channel capacitance CGC varies nonlinearly with gate-source voltage:

$$ C_{GC} = C_{ox}WL \left[1 - \left(\frac{V_{GS} - V_{TH}}{V_{GS} - V_{TH} + 2\phi_F}\right)^{1/2}\right] $$

Quantitative Analysis

The total error voltage ΔV at the sampling node combines both effects:

$$ \Delta V = \underbrace{\frac{C_{ov}}{C_{ov} + C_S}V_{CLK}}_{\text{Clock feedthrough}} + \underbrace{\frac{\alpha Q_{ch}}{C_S}}_{\text{Charge injection}} $$

where α (typically 0.5-1.0) represents the charge partitioning factor, Cov is the overlap capacitance, CS the sampling capacitance, and Qch the channel charge:

$$ Q_{ch} = WLC_{ox}(V_{GS} - V_{TH}) $$

Mitigation Techniques

Advanced circuit techniques address these errors:

MOS Switch CGD, CGS

Process-Dependent Considerations

In deep-submicron technologies, secondary effects become significant:

The error voltage shows technology scaling dependence:

$$ \frac{\Delta V}{V_{FS}} \propto \frac{1}{C_S}\left(\frac{C_{ov}}{L} + \frac{C_{ox}W}{2}\right) $$

where VFS represents the full-scale voltage range. This relationship drives the increasing adoption of metal-insulator-metal (MIM) capacitors in advanced nodes for their superior matching and linearity characteristics.

MOS Switch Parasitics and Charge Injection Schematic of a MOS transistor switch showing parasitic capacitances (C_GD, C_GS) and charge injection paths during turn-off. Gate (V_CLK) Source Drain C_GS C_GD Q_ch
Diagram Description: The diagram would show the physical MOS switch structure with parasitic capacitances (C_GD, C_GS) and charge injection paths during turn-off.

5.3 Low-Voltage and Low-Power SC Circuits

Challenges in Low-Voltage Operation

Traditional switched-capacitor (SC) circuits rely on high overdrive voltages to ensure proper switch operation and charge transfer. However, as supply voltages scale down to sub-1V levels, MOSFET switches exhibit significant non-idealities:

$$ I_D = \mu_n C_{ox} \frac{W}{L} \left( (V_{GS} - V_{TH})V_{DS} - \frac{V_{DS}^2}{2} \right) $$

At low VGS, Ron increases quadratically, degrading settling time and charge transfer accuracy.

$$ I_{leak} = I_0 e^{\frac{V_{GS} - V_{TH}}{nV_T}} \left(1 - e^{-\frac{V_{DS}}{V_T}}\right) $$

Low-Voltage Switch Techniques

Bootstrapped Switches

Bootstrapping maintains constant VGS across the switch transistor regardless of input signal level. A floating capacitor charged to VDD drives the gate:

Msw Vin Vout

Clock Voltage Doubling

Charge pumps generate higher clock amplitudes (2VDD) to ensure sufficient overdrive. The power overhead is given by:

$$ P_{CP} = f_{sw} \cdot C_{fly} \cdot (2V_{DD})^2 $$

Low-Power Design Strategies

Charge Recycling

Reusing charge between phases reduces dynamic power dissipation. The theoretical minimum energy per conversion is:

$$ E_{min} = kT \ln(2) $$

Subthreshold Operation

Biasing transistors in weak inversion reduces power but increases sensitivity to PVT variations. The transconductance efficiency (gm/ID) peaks in this region:

$$ \frac{g_m}{I_D} = \frac{1}{nV_T} $$

Advanced Architectures

Time-domain processing techniques like pulse-width modulation (PWM) or time-based ADCs eliminate static current paths. The resolution is determined by:

$$ \Delta t = \frac{V_{in} \cdot C}{I_{ref}} $$

Recent implementations in 65nm CMOS achieve 8-bit resolution at 1MS/s with 380nW power consumption.

Noise Considerations

kT/C noise remains a fundamental limit, but flicker noise becomes dominant at low frequencies. Correlated double sampling (CDS) mitigates this by storing noise samples:

$$ \overline{v_{n,out}^2} = \frac{kT}{C} \left(1 + \frac{1}{\alpha}\right) $$

where α is the charge transfer efficiency.

Bootstrapped Switch and Charge Pump Circuit Schematic diagram illustrating a bootstrapped MOSFET switch (left) and a charge pump circuit (right) with labeled components and signal flow. M_sw V_in V_out C_boot V_DD C_fly1 C_fly2 V_out Φ1 Φ2 Bootstrapped Switch Charge Pump Signal Flow
Diagram Description: The section explains bootstrapped switches and clock voltage doubling, which involve specific circuit configurations and charge transfer mechanisms that are best visualized.

6. Key Research Papers and Books

6.1 Key Research Papers and Books

6.2 Online Resources and Tutorials

6.3 Simulation Tools and Design Kits