Tape recorder interface

The interface enables data to be recorded on a standard tape recorder at a speed of 2400 bits per second. The serial data stream is encoded with a clock frequency of 2400 Hz using an XOR gate (IC 1/1). The resulting logical "high" and "low" signals are illustrated in the accompanying figures. These signals are then attenuated and fed into the recording input of a cost-effective tape recorder. During playback, the pulses are amplified using a CMOS gate (IC 1/2) configured as a linear amplifier, producing a TTL level signal. Both positive and negative transitions are processed by IC 1/4, which generates short pulses that trigger a one-shot timer (IC 2). The width of the monostable pulse is set to three times the bit length (310 µs). A transition from "high" to "low" in the coded stream results in a "low" pulse width equivalent to one bit cell, while a transition from "low" to "high" generates a "high" pulse of the same duration. During this pulse, the one-shot latches the state of the line in a D-type flip-flop (IC 3). When the data stream contains consecutive "ones" or "zeros," the one-shot is retriggered before the quasistable state concludes, maintaining the flip-flop's state. The original data stream is available at the output of the flip-flop. The Z80 DUART receiving these pulses is programmed to operate with a receiver clock that is 16 times the data rate (38.4 kHz).

The described circuit utilizes a series of integrated circuits (ICs) to facilitate the encoding and decoding of data for storage on magnetic tape. The XOR gate (IC 1/1) is essential for modulating the data stream with the clock signal, ensuring that the recorded signals maintain synchronization with the timing reference. The amplitude adjustment before sending the signal to the tape recorder is crucial, as it prevents distortion and ensures reliable playback.

During playback, the CMOS gate (IC 1/2) amplifies the incoming pulses to a level suitable for further processing. The linear amplifier configuration allows for a faithful reproduction of the recorded data, ensuring that the TTL signal levels are achieved for subsequent digital processing.

The use of IC 1/4 to create short pulses upon detecting transitions in the signal is an effective method for capturing the rapid changes in the data stream. This functionality is critical for accurately representing the original data, especially in sequences of identical bits, where the one-shot timer (IC 2) must be retriggered to avoid missing transitions.

The D-type flip-flop (IC 3) serves as a memory element, capturing the state of the data stream at precise moments dictated by the pulse widths generated by IC 2. This allows for the reconstruction of the original data sequence at the output, which can then be processed by the Z80 DUART. The configuration of the DUART to operate at 38.4 kHz, which is 16 times the data rate, ensures that the data can be reliably received and processed without errors, facilitating efficient communication in digital systems. Overall, this circuit design showcases a practical approach to data storage and retrieval using analog media, leveraging digital logic components to achieve reliable performance.The interface allows data to be saved on an ordinary tape recorder at a speed of 2400 bit/s. The serial stream of data Fig. 1 (A) is coded with a clock of 2400 Hz (B), by means of XOR gate IC 1/1. Logical "high" and "low" appear as shown in Fig. 2 (C). These impulses are lowered in amplitude and feed into the record input of a low cost tape recorder. During the playback, pulses (D) are amplified with CMOS gate IC 1/2 connected as a linear amplifier, and providing a TTL level signal shown in (E). On both positive and negative transitions IC 1/4 forms short pulses as shown in (F) (approx. 50 *ts) that triggers one shot IC2. A monostable one shot pulse width is adjusted to be 3A of bit length (310 µß). A change from "high" to "low" in a coded stream generates a "low" pulse width of one bit cell. The same is for change from ' low'' to ' 'high'' that generates a "high" pulse of the same width. During this pulse one shot latches the state of line in D type flip-flop IC3 (G). When a stream consists of multiple "ones" or "zeros," the one shot is retriggered before it comes to the end of the quasistable state and the state of the flip-flop remains unchanged. The original data stream is available at the output of the flip-flop (). Z80 the DUART that receives these pulses is programmed so that the receiver clock is 16 times the data rate (38.4 kHz).

🔗 External reference