The circuit consists of 6 building blocks and the first is the inverter between pins 1 and 2. This forms a low frequency oscillator with a 1u and 1M + 2M2 resistor. It governs the overall timing of the ring by creating an ON and OFF time. When the output is LOW, the tone is emitted from the piezo. When the output is HIGH, the tone is inhibited and this produces the silence between the rings. This oscillator has an equal mark-space ratio to give the `rings` the same length of time as the silence. The second oscillator operates at about twice the frequency of the first (this can be seen by the different value of the resistors as both capacitors have the same value).
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The frequency has been adjusted so that it produces two highs during the interval when it is activated. The second oscillator does not produce two full cycles but only one and a half as it is the HIGHs that are required.
During each of these HIGHs, the third and fourth oscillators produce a warble that simulates the 33Hz ring of the "bell." The third oscillator generates the 33Hz frequency and this gates the fourth oscillator to produce a 1kHz tone for the piezo. The output of this oscillator drives the base of the buffer transistor and also one side of the piezo. The other side of the piezo is connected to the output of two buffers in parallel and this provides good pull-down capability when the left side of the piezo is high.
The only fault in the design of this circuit is the drive to the left-hand side of the piezo. We should have included driving buffers to give it the maximum swing and thus the maximum output. But since we did not have any left over, this is the best we could do.
When the piezo is driven from a pair of buffers on each side, it sees a voltage swing of nearly twice the rail voltage and this gives it the highest output.
The tone is also passed to a LED via a transistor to give a visual indication of the operation of the circuit.
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