Multiplexers and Demultiplexers

#multiplexers #demultiplexers #digital systems #logic diagrams #truth tables #ICs #analog multiplexers #digital multiplexers #hybrid multiplexers #practical implementation

1. Definition and Basic Concepts

Definition and Basic Concepts

A multiplexer (MUX) is a combinational logic circuit that selects one of several input signals and forwards it to a single output line. The selection is controlled by a set of select lines, which determine which input is connected to the output at any given time. Mathematically, an n-input multiplexer requires k select lines, where:

$$ k = \lceil \log_2 n \rceil $$

For example, a 4:1 multiplexer (4 inputs, 1 output) requires 2 select lines, since \(2^2 = 4\). The truth table for a 4:1 MUX is as follows:

S1 S0 Output (Y)
0 0 I0
0 1 I1
1 0 I2
1 1 I3

The Boolean expression for the output Y of a 4:1 MUX is derived as:

$$ Y = \overline{S_1} \overline{S_0} I_0 + \overline{S_1} S_0 I_1 + S_1 \overline{S_0} I_2 + S_1 S_0 I_3 $$

Demultiplexers (DEMUX)

A demultiplexer (DEMUX) performs the inverse operation of a multiplexer. It takes a single input and routes it to one of several output lines based on the select lines. A 1:4 demultiplexer, for instance, has 1 input, 4 outputs, and 2 select lines. The output equations for a 1:4 DEMUX are:

$$ \begin{align*} Y_0 &= \overline{S_1} \overline{S_0} \cdot D \\ Y_1 &= \overline{S_1} S_0 \cdot D \\ Y_2 &= S_1 \overline{S_0} \cdot D \\ Y_3 &= S_1 S_0 \cdot D \\ \end{align*} $$

Practical Applications

Multiplexers and demultiplexers are fundamental in digital communication systems, where they enable efficient data routing. Key applications include:

Implementation in Digital Systems

In CMOS technology, multiplexers are often implemented using transmission gates or a combination of AND-OR logic. A 2:1 MUX can be constructed with two transmission gates controlled by complementary select signals:

$$ Y = S \cdot I_0 + \overline{S} \cdot I_1 $$

For higher-order multiplexers, a tree structure of smaller MUX units (e.g., cascading 2:1 MUXes) is commonly employed to optimize propagation delay and transistor count.

This section provides a rigorous, mathematically grounded explanation of multiplexers and demultiplexers while maintaining readability and logical flow. The HTML is well-structured, all tags are properly closed, and equations are formatted in LaTeX within `
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Definition and Basic Concepts in Multiplexers and Demultiplexers
Diagram Description: A diagram would visually show the input/output relationships and selection logic of a 4:1 MUX and 1:4 DEMUX, which are spatial concepts.

Key Differences Between Multiplexers and Demultiplexers

Functional Operation

A multiplexer (MUX) is a combinational circuit that selects one of multiple input lines and directs it to a single output line based on the control signals. The selection is governed by the following Boolean logic:

$$ Y = \sum_{i=0}^{2^n-1} (D_i \cdot S_i) $$

where Y is the output, Di are the data inputs, and Si are the select lines (n = log2(number of inputs)). In contrast, a demultiplexer (DEMUX) performs the inverse operation: it takes a single input and routes it to one of multiple outputs based on the select lines. The output logic for a 1-to-4 DEMUX is:

$$ O_j = I \cdot \prod_{k=0}^{n-1} (S_k^{b_k}) $$

where Oj is the jth output, I is the input, and bk are the binary-encoded bits of j.

Directionality and Signal Flow

Multiplexers are inherently many-to-one devices, consolidating multiple data streams into one. This makes them essential in time-division multiplexing (TDM) systems, where they enable bandwidth efficiency by interleaving signals. Demultiplexers, however, are one-to-many devices, critical for reconstructing parallel data from serial streams in communication receivers. The bidirectional nature of some modern ICs (e.g., 74HC4051) blurs this distinction by integrating both functions.

Control Signal Interpretation

While both use select lines, their interpretation differs:

The truth table for a 2:1 MUX (S = select, D0, D1 = inputs) shows Y = D0S' + D1S, whereas a 1:2 DEMUX satisfies O0 = I·S' and O1 = I·S.

Practical Implementations

In telephony, MUX/DEMUX pairs enable PCM (Pulse Code Modulation) systems to share transmission lines. A 8:1 MUX might sample 8 voice channels at 8 kHz, while the paired DEMUX reconstructs them using synchronized select signals. Timing mismatches cause intersymbol interference, mitigated by clock recovery circuits in the DEMUX.

Integrated Circuit Examples

The 74LS151 (8:1 MUX) and 74LS138 (3:8 DEMUX) illustrate key differences:

Mathematical Duality

MUX and DEMUX exhibit duality in Boolean algebra. A 2n:1 MUX can implement any n-input logic function by tying inputs to constants (universal logic property), while a 1:2n DEMUX with an OR gate at each output can implement a canonical sum-of-products form.

Key Differences Between Multiplexers and Demultiplexers in Multiplexers and Demultiplexers
Diagram Description: A diagram would visually contrast the signal flow and structural differences between multiplexers and demultiplexers, which are inherently spatial concepts.

1.3 Common Applications in Digital Systems

Data Routing and Signal Switching

Multiplexers (MUX) are widely used in digital systems for efficient data routing, where multiple input signals share a single transmission line or processing unit. A 2n-to-1 MUX selects one of 2n inputs using n control lines. For example, an 8-to-1 MUX (3 select lines) can dynamically route one of eight sensor inputs to a single ADC in a data acquisition system. This minimizes hardware complexity while maintaining signal integrity.

$$ Y = \sum_{i=0}^{2^n-1} (D_i \cdot S_i) $$

Here, Y is the output, Di represents input data lines, and Si are the minterms derived from select lines. This Boolean summation ensures only the selected input propagates to the output.

Memory Addressing and Bank Selection

High-speed memory systems employ MUX/DEMUX pairs to reduce address line congestion. A 1-to-4 demultiplexer (DEMUX) splits a single address bus into four memory banks, enabling efficient bank switching without additional CPU pins. Modern DDR5 controllers use hierarchical MUX networks to manage 64-bit data paths across multiple channels.

Arithmetic Logic Unit (ALU) Control

In processor design, MUXes select between arithmetic (e.g., adder outputs) and logical operations (e.g., AND/XOR) within the ALU. A 4-to-1 MUX with opcode-controlled selection lines can implement basic instruction sets. For instance:

$$ \text{ALU}_{out} = \begin{cases} A + B & \text{if } S_1S_0 = 00 \\ A \oplus B & \text{if } S_1S_0 = 01 \\ A \cdot B & \text{if } S_1S_0 = 10 \\ \overline{A} & \text{if } S_1S_0 = 11 \end{cases} $$

Time-Division Multiplexing (TDM)

Telecommunication systems leverage TDM to interleave multiple digital signals onto a single carrier. A synchronous MUX-DEMUX pair, clocked at the Nyquist rate, allocates fixed time slots to each channel. SONET networks, for example, use STS-1 frames with 810-byte payloads distributed across 28 TDM channels.

FPGA Configuration and I/O Expansion

Field-programmable gate arrays (FPGAs) integrate thousands of MUXes to implement reconfigurable logic blocks (CLBs). Each lookup table (LUT) in a Xilinx 7-series FPGA is essentially a 16-to-1 MUX programmed via SRAM cells. Similarly, DEMUXes expand limited I/O pins to interface with multiple peripherals through serial-to-parallel conversion.

Error Detection and Correction

Demultiplexers assist in syndrome decoding for error-correcting codes (ECC). A (7,4) Hamming code decoder uses a 3-to-8 DEMUX to map syndrome bits to specific error locations, enabling single-bit error correction. The Boolean equivalence for syndrome S is:

$$ E = S_2S_1S_0 $$

where E activates the corrective XOR gate at the erroneous bit position.

High-Speed Serialization

Serializer/deserializer (SerDes) circuits in PCIe and USB4 protocols employ MUX trees to parallelize data. A 16:1 serialization MUX combines 16 parallel lanes into a single 64 Gbps PAM4 signal, while clock-and-data recovery (CDR) DEMUXes reconstruct the original lanes at the receiver.

16:1 MUX 64 Gbps PAM4

2. Working Principle of Multiplexers

Working Principle of Multiplexers

A multiplexer (MUX) is a combinational logic circuit that selects one of several input signals and forwards it to a single output line. The selection is controlled by a set of select lines, which determine which input is connected to the output at any given time. Mathematically, an n-input multiplexer requires k select lines, where k = log2n.

Functional Representation

The operation of a 4:1 multiplexer can be expressed using Boolean algebra. Let the inputs be D0, D1, D2, and D3, with select lines S1 and S0. The output Y is given by:

$$ Y = \overline{S_1}\overline{S_0}D_0 + \overline{S_1}S_0D_1 + S_1\overline{S_0}D_2 + S_1S_0D_3 $$

This equation represents the logical OR of all possible input-select combinations. Each product term corresponds to one input being selected when the appropriate combination of select lines is active.

Internal Architecture

The core of a multiplexer consists of:

4:1 Multiplexer D₀ D₁ D₂ D₃ Y S₀ S₁

Propagation Delay Analysis

The worst-case propagation delay (tpd) in a multiplexer is determined by the critical path through the logic gates. For an n:1 MUX implemented with two-level logic:

$$ t_{pd} = t_{AND} + t_{OR} $$

where tAND and tOR are the propagation delays of the AND and OR gates respectively. In CMOS implementations, this delay scales with the fan-in due to increased parasitic capacitance.

Applications in Digital Systems

Advanced Implementations

Modern IC designs often use transmission gate-based multiplexers for reduced power consumption and improved speed. The on-resistance (Ron) of the transmission gates introduces an RC delay:

$$ \tau = R_{on}C_{load} $$

where Cload is the total capacitance at the output node. This architecture is particularly advantageous in low-voltage designs where threshold voltage drops become significant in pass-transistor implementations.

Working Principle of Multiplexers in Multiplexers and Demultiplexers
Diagram Description: The diagram would physically show the internal architecture of a 4:1 multiplexer, including input lines, select lines, and the AND-OR gate network.

2.2 Types of Multiplexers (Analog, Digital, and Hybrid)

Analog Multiplexers

Analog multiplexers (AMUX) route continuous-time signals from multiple input channels to a single output line. These devices rely on solid-state switches—typically MOSFETs or JFETs—to maintain signal integrity with minimal distortion. The on-resistance (RON) and off-capacitance (COFF) of these switches critically impact performance metrics like bandwidth and crosstalk.

$$ \text{Bandwidth} = \frac{1}{2\pi R_{ON}C_{OFF}} $$

Key parameters include:

Applications span medical instrumentation (EEG/ECG systems) and automotive sensor networks where preserving analog signal fidelity is paramount.

Digital Multiplexers

Digital multiplexers (MUX) select binary inputs using control lines governed by Boolean algebra. An n-to-1 MUX requires k select lines where k = log2n. The canonical implementation uses AND-OR logic gates:

$$ Y = \sum_{i=0}^{n-1} (D_i \cdot S_i) $$

where Di are data inputs and Si are minterms from select lines. Propagation delay (tpd) scales with CMOS technology nodes—contemporary 7nm ASICs achieve delays below 50 ps.

Advanced variants include:

Hybrid Multiplexers

Hybrid designs merge analog switching with digital control, exemplified by RF MUX ICs such as the SKY13370-385LF. These devices handle signals up to 6 GHz while being controlled via I2C or SPI interfaces. Critical design challenges include:

Such multiplexers enable software-defined radio (SDR) and phased-array radar systems where both analog performance and digital configurability are essential.

Performance Tradeoffs

The selection matrix below compares key metrics across multiplexer types:

Parameter Analog Digital Hybrid
Signal Type Continuous Discrete Both
Switching Speed ~100 ns ~1 ns ~10 ns
Power Consumption μW-mW nW-μW mW-W

Emerging technologies like MEMS-based optical MUX devices push these boundaries further, achieving sub-nanosecond switching with >100 dB isolation in research prototypes.

Types of Multiplexers (Analog, Digital, and Hybrid) in Multiplexers and Demultiplexers
Diagram Description: A diagram would physically show the internal structure of analog, digital, and hybrid multiplexers, highlighting their key components and signal flow paths.

2.3 Truth Tables and Logic Diagrams

Truth Tables for Multiplexers

A multiplexer (MUX) selects one of N input lines and routes it to a single output based on a set of control signals. For an n-bit selector, the MUX has 2n input lines. The truth table for a 4-to-1 MUX (n = 2) is constructed as follows:

$$ \text{Output } Y = \overline{S_1} \overline{S_0} I_0 + \overline{S_1} S_0 I_1 + S_1 \overline{S_0} I_2 + S_1 S_0 I_3 $$
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Here, S1 and S0 are the selector inputs, while I0 to I3 are the data inputs. The output Y follows the selected input based on the selector combination.

Logic Diagram of a 4-to-1 MUX

The logic implementation of a 4-to-1 MUX consists of AND gates for input selection and an OR gate for output combination. Each AND gate is enabled only when the corresponding selector condition is met:

Decoder AND AND AND AND OR Y

The decoder generates minterms from the selector inputs, which activate the respective AND gates. The OR gate combines the outputs of all AND gates to produce Y.

Truth Tables for Demultiplexers

A demultiplexer (DEMUX) performs the inverse operation of a MUX, routing a single input to one of 2n outputs based on the selector lines. The truth table for a 1-to-4 DEMUX is:

S1 S0 D0 D1 D2 D3
0 0 I 0 0 0
0 1 0 I 0 0
1 0 0 0 I 0
1 1 0 0 0 I

Here, I is the input signal, and D0 to D3 are the outputs. Only one output is active at a time, determined by the selector combination.

Logic Diagram of a 1-to-4 DEMUX

The DEMUX logic structure resembles a decoder with an enable input. Each output is driven by an AND gate combining the input signal with a decoded selector term:

I AND AND AND AND D0 D1 D2 D3

The selector inputs S1 and S0 determine which output line (D0 to D3) receives the input signal I.

Truth Tables and Logic Diagrams in Multiplexers and Demultiplexers
Diagram Description: The logic diagrams visually demonstrate how selector inputs control AND/OR gate configurations to route signals in MUX/DEMUX circuits, which is spatial and structural.

2.4 Practical Implementation and ICs

Standard Logic IC Families for Multiplexing

Modern digital systems implement multiplexers and demultiplexers using standardized IC families. The 74-series TTL and 4000-series CMOS remain prevalent, with key differences in voltage levels, power consumption, and switching speeds. The 74HC series (High-speed CMOS) offers optimal balance, typically operating at 2-6V with propagation delays under 10ns. For high-speed applications, 74AC/74ACT variants achieve sub-5ns delays while maintaining CMOS voltage compatibility.

$$ t_{pd} = R_{on}C_{load} + t_{intrinsic} $$

where Ron represents the ON-resistance of switching transistors and Cload the parasitic capacitance.

Common Multiplexer ICs

The 74HC151 demonstrates typical characteristics: 5.2mA output drive at 4.5V, 23ns propagation delay, and 20μA quiescent current. Its internal structure uses three-level AND-OR-Invert (AOI) logic gates to implement the selection logic:

$$ Y = \sum_{i=0}^{7} (D_i \cdot S_2'S_1'S_0') $$

where S2:0 are selection bits and Di data inputs.

Demultiplexer IC Implementations

Demultiplexers often share silicon with decoders - the 74HC138 serves as both a 3:8 decoder and 1:8 demux. Key parameters include output enable timing (typically 15-30ns) and fan-out capability (up to 10 LSTTL loads). The 74HC238 variant features active-high outputs for bus driving applications.

High-Density Multiplexing Solutions

For systems requiring >16 channels, cascaded designs using enable pins or specialized ICs like the 74HC4067 (16:1 analog mux) become necessary. Propagation delay accumulates in cascaded configurations:

$$ t_{total} = \sum_{i=1}^{n} t_{pd,i} + (n-1)t_{skew} $$

PCB Layout Considerations

High-speed multiplexing requires careful routing to minimize crosstalk and signal degradation. Critical practices include:

For RF applications above 100MHz, ICs like the MAX4784 (500MHz bandwidth) employ specialized architectures with distributed amplifiers and transmission line matching.

Programmable Logic Implementations

FPGAs and CPLDs implement multiplexers using look-up tables (LUTs). A 4:1 mux requires one 4-input LUT in most architectures. Modern synthesis tools optimize large multiplexers into specialized carry-chain resources when available, achieving sub-nanosecond routing delays.

3. Working Principle of Demultiplexers

Working Principle of Demultiplexers

A demultiplexer (DEMUX) is a combinational logic circuit that routes a single input signal to one of several output lines based on the values of its select lines. Its operation is functionally inverse to that of a multiplexer (MUX). While a MUX consolidates multiple inputs into a single output, a DEMUX distributes a single input across multiple outputs.

Functional Model

The fundamental operation of a demultiplexer can be described by a truth table mapping input and select lines to outputs. For an n-select-line DEMUX:

$$ Y_k = D \cdot \prod_{i=0}^{n-1} S_i^{b_i} $$

where bi is the i-th bit of the binary representation of k, and Sibi denotes the select line in asserted (1) or negated (0) form.

Implementation Using Logic Gates

A 1-to-4 demultiplexer can be constructed using two select lines (S0, S1), four AND gates, and two NOT gates. The output equations are:

$$ Y_0 = D \cdot \overline{S_1} \cdot \overline{S_0} $$ $$ Y_1 = D \cdot \overline{S_1} \cdot S_0 $$ $$ Y_2 = D \cdot S_1 \cdot \overline{S_0} $$ $$ Y_3 = D \cdot S_1 \cdot S_0 $$

This implementation scales exponentially with additional select lines, requiring 2n AND gates for an n-select-line DEMUX.

Time-Domain Behavior

The propagation delay (tpd) of a demultiplexer is critical in high-speed systems and consists of:

The worst-case delay occurs when both select and data signals change simultaneously:

$$ t_{pd} = \max(t_{s2y}, t_{d2y}) + t_{setup} $$

Applications in Digital Systems

Demultiplexers find extensive use in:

Cascading Demultiplexers

Large demultiplexers can be constructed by cascading smaller units. A 1-to-16 DEMUX can be implemented using five 1-to-4 demultiplexers:

The hierarchical approach optimizes gate utilization at the cost of increased propagation delay through multiple stages.

Power Considerations

CMOS demultiplexers exhibit power dissipation dominated by:

$$ P_{total} = P_{dynamic} + P_{static} $$ $$ P_{dynamic} = \alpha C_L V_{DD}^2 f $$

where α is the activity factor, CL is load capacitance, VDD is supply voltage, and f is switching frequency. Advanced implementations use:

Working Principle of Demultiplexers in Multiplexers and Demultiplexers
Diagram Description: The section describes a 1-to-4 demultiplexer implementation using logic gates and cascading multiple demultiplexers, which are highly visual concepts.

3.2 Types of Demultiplexers

Demultiplexers (DEMUX) are combinational logic circuits that route a single input signal to one of multiple output lines based on the selection inputs. The choice of DEMUX architecture depends on factors such as speed, power consumption, and application-specific requirements. Below are the primary types of demultiplexers used in digital systems.

1-to-4 Line Demultiplexer

A 1-to-4 DEMUX has one input line (D), two selection lines (S0 and S1), and four output lines (Y0 to Y3). The Boolean logic for each output is derived as follows:

$$ Y_0 = D \cdot \overline{S_1} \cdot \overline{S_0} $$ $$ Y_1 = D \cdot \overline{S_1} \cdot S_0 $$ $$ Y_2 = D \cdot S_1 \cdot \overline{S_0} $$ $$ Y_3 = D \cdot S_1 \cdot S_0 $$

This configuration is commonly implemented using AND gates and inverters. In high-speed applications, transmission gate-based designs reduce propagation delay.

1-to-8 Line Demultiplexer

Extending the concept, a 1-to-8 DEMUX uses three selection lines (S0 to S2) to route the input to one of eight outputs. The logic equations follow a similar pattern:

$$ Y_n = D \cdot \overline{S_2} \cdot \overline{S_1} \cdot \overline{S_0} \quad \text{(for n=0)} $$ $$ \vdots $$ $$ Y_7 = D \cdot S_2 \cdot S_1 \cdot S_0 $$

Cascading two 1-to-4 DEMUXes with an additional selection line achieves this functionality. This architecture is prevalent in memory address decoding.

Serial-to-Parallel Converter DEMUX

Unlike conventional DEMUXes, serial-to-parallel converters distribute sequential input bits across parallel outputs. A shift register combined with a counter serves as the selection mechanism. The timing diagram shows:

This type finds applications in data communication systems where serial data streams need conversion to parallel format for processing.

High-Speed Current-Mode DEMUX

For GHz-range operations, current-mode logic (CML) DEMUXes offer superior performance. The differential pair topology minimizes voltage swings, enabling faster switching. The key parameters are:

$$ t_{pd} = \frac{C_L \Delta V}{I_{SS}} $$

where CL is load capacitance, ΔV is voltage swing, and ISS is tail current. These DEMUXes are integral to optical communication receivers.

Wavelength Division Demultiplexer

In fiber optics, WDM DEMUXes separate light by wavelength using either:

The channel spacing Δλ follows from the grating equation:

$$ m\lambda = d(\sin\alpha + \sin\beta) $$

where m is diffraction order, d is grating period, and α,β are incidence/refraction angles. Modern DWDM systems handle 80+ channels with 50GHz spacing.

Types of Demultiplexers in Multiplexers and Demultiplexers
Diagram Description: The section describes multiple demultiplexer architectures with logical relationships and signal routing that would benefit from visual representation.

3.3 Truth Tables and Logic Diagrams

Truth Tables for Multiplexers and Demultiplexers

Truth tables provide a complete functional representation of multiplexers (MUX) and demultiplexers (DEMUX) by enumerating all possible input combinations and their corresponding outputs. For an n-input MUX with m select lines (n = 2m), the truth table has 2m + m columns (inputs + select lines) and 2m+k rows, where k is the number of control bits.

$$ \text{Output} = \sum_{i=0}^{n-1} (I_i \cdot S_i) $$

where Ii represents input lines and Si is the product of select line states that enable input i. For a 4:1 MUX:

S1 S0 Output (Y)
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Logic Diagram Construction

Multiplexer logic diagrams consist of three key components:

A 2:1 MUX implements the Boolean function:

$$ Y = (I_0 \cdot \overline{S}) + (I_1 \cdot S) $$

For demultiplexers, the logic reverses - a single input routes to one of 2m outputs based on select lines. A 1:4 DEMUX truth table shows:

S1 S0 Enabled Output
0 0 Y0 = Input
0 1 Y1 = Input
1 0 Y2 = Input
1 1 Y3 = Input

Practical Implementation Considerations

CMOS implementations typically use transmission gates for MUX/DEMUX designs due to their bidirectional nature and low ON resistance. Propagation delay (tpd) scales logarithmically with the number of inputs:

$$ t_{pd} = t_{gate} \cdot \lceil \log_2 n \rceil $$

where tgate is the delay per logic level. Modern FPGAs implement MUX/DEMUX functions using lookup tables (LUTs), where a 6-input LUT can realize any 4:1 MUX or 1:16 DEMUX configuration.

I₀ I₁ I₂ I₃ Y S₀ S₁ 4:1 MUX
Truth Tables and Logic Diagrams in Multiplexers and Demultiplexers
Diagram Description: The section describes the internal logic structure of multiplexers and demultiplexers, which requires visualization of AND/OR gate arrangements and select line decoding.

3.4 Practical Implementation and ICs

Integrated Circuit Multiplexers and Demultiplexers

Modern digital systems rely heavily on integrated circuits (ICs) to implement multiplexers (MUX) and demultiplexers (DEMUX) efficiently. These ICs are optimized for speed, power consumption, and physical footprint, making them indispensable in high-performance applications. Common logic families include TTL (74-series) and CMOS (4000-series, 74HC-series), each offering trade-offs between propagation delay and power dissipation.

Standard MUX/DEMUX ICs

The 74HC151 is a classic 8:1 multiplexer with complementary outputs, while the 74HC138 serves as a 3:8 demultiplexer. These ICs operate at CMOS voltage levels (2V to 6V) and exhibit propagation delays under 10 ns. For larger configurations, cascading is achieved using enable pins or additional control logic. The truth table for a 74HC151 is given by:

$$ Y = \overline{E} \cdot \sum_{i=0}^{7} (D_i \cdot m_i) $$ $$ \overline{W} = \overline{Y} $$

where E is the enable input, Di are data inputs, and mi are minterms derived from the select lines S2S1S0.

Analog Multiplexers

Analog variants like the CD4051 (8:1) and ADG708 (8:1 low-RON) handle continuous signals. Key parameters include:

Layout Considerations

PCB design for MUX/DEMUX ICs must address:

Case Study: Memory Addressing

In DRAM systems, a single 16:1 MUX (e.g., SN74CBT16292) reduces address bus width by 4×. The select lines are driven by a counter, while the DEMUX (e.g., MC74HC259) reconstructs the full address at the memory bank. Timing analysis reveals:

$$ t_{setup} = t_{MUX\_delay} + t_{wire\_delay} + t_{DEMUX\_delay} < t_{clock} - t_{jitter} $$

Advanced ICs: FPGA and ASIC Implementations

Modern FPGAs integrate hardened MUX/DEMUX blocks in their I/O banks and routing matrices. Xilinx 7-series devices use CLBs (Configurable Logic Blocks) with 4:1 MUXes in each LUT, while Intel Stratix 10 employs ALMs (Adaptive Logic Modules) featuring 6-input fracturable MUXes. ASIC implementations often optimize for:

Practical Implementation and ICs in Multiplexers and Demultiplexers
Diagram Description: The section covers IC pinouts, signal routing, and timing relationships that are inherently spatial.

4. Time-Division Multiplexing (TDM)

4.1 Time-Division Multiplexing (TDM)

Time-Division Multiplexing (TDM) is a method of transmitting multiple independent signals over a single communication channel by dividing the transmission time into discrete time slots. Each input signal is allocated a specific time interval, during which it occupies the full bandwidth of the channel. This technique is widely used in digital telephony, optical communications, and high-speed data networks.

Fundamental Principles

TDM operates by interleaving samples from multiple low-rate data streams into a single high-rate stream. The multiplexer cycles through each input in sequence, transmitting a fixed-duration sample before switching to the next. At the receiver, the demultiplexer synchronously reconstructs the original signals by extracting samples from their assigned time slots.

$$ T_s = \sum_{i=1}^{N} t_i $$

where Ts is the total frame duration, N is the number of channels, and ti is the time slot allocated to the i-th channel. The Nyquist sampling theorem dictates that each signal must be sampled at least twice its highest frequency component to avoid aliasing.

Synchronization and Guard Bands

Accurate synchronization is critical in TDM systems to prevent intersymbol interference (ISI). A synchronization pulse or unique framing pattern is often embedded in the data stream to align the demultiplexer. Guard bands—small time intervals between slots—compensate for timing jitter and propagation delays.

$$ t_g = \frac{T_s}{N} \cdot \alpha $$

Here, tg is the guard time, and α is a design parameter typically between 0.1 and 0.2. Excessive guard bands reduce efficiency, while insufficient margins risk data corruption.

Applications and Variants

In modern networks, TDM often coexists with wavelength-division multiplexing (WDM) to maximize fiber capacity. For instance, the SONET/SDH standards use TDM hierarchies (STS-1, STM-1) to aggregate voice and data traffic.

Performance Limitations

The maximum channel count N in a TDM system is constrained by:

$$ N \leq \frac{B}{2B_i} $$

where B is the channel bandwidth and Bi is the bandwidth of an individual signal. Nonlinear effects in optical fibers and clock skew in electrical systems further limit practical implementations.

Frame N Ch 1 Ch 2 Ch 3 Ch 4 Sync Pulse
Time-Division Multiplexing (TDM) in Multiplexers and Demultiplexers
Diagram Description: The diagram would physically show how time slots are interleaved in a TDM frame with labeled channels, sync pulse, and guard bands.

4.2 Frequency-Division Multiplexing (FDM)

Frequency-division multiplexing (FDM) is an analog multiplexing technique that combines multiple signals by assigning each a distinct carrier frequency within a shared transmission medium. The principle relies on the orthogonality of sinusoidal signals—when carrier frequencies are sufficiently spaced, the modulated signals remain separable at the receiver.

Mathematical Foundation

Consider N baseband signals xi(t), each bandlimited to B Hz. To multiplex them, each signal modulates a carrier frequency fi with a guard band Δf to prevent spectral overlap. The composite signal s(t) is:

$$ s(t) = \sum_{i=1}^{N} x_i(t) \cos(2\pi f_i t + \phi_i) $$

where ϕi is the phase offset. The minimum required bandwidth W for the multiplexed signal is:

$$ W = N \cdot B + (N - 1) \cdot \Delta f $$

Demodulation at the receiver involves coherent detection using a bank of bandpass filters centered at each fi, followed by a low-pass filter to recover the baseband signal.

Practical Implementation

FDM systems employ subcarrier allocation to optimize spectrum usage. Key design parameters include:

Applications and Case Studies

FDM is foundational in legacy telephony (e.g., AT&T’s L-carrier system) and broadcast radio. Modern applications include:

Limitations and Trade-offs

FDM suffers from nonlinear distortion in amplifiers due to intermodulation products. Additionally, guard bands reduce spectral efficiency compared to time-division multiplexing (TDM) in digital systems.

Channel 1 (f₁) Channel 2 (f₂) Channel 3 (f₃) Composite FDM Spectrum
Frequency-Division Multiplexing (FDM) in Multiplexers and Demultiplexers
Diagram Description: The diagram would physically show the composite FDM spectrum with distinct frequency channels and guard bands.

4.3 Use in Communication Systems

Time-Division Multiplexing (TDM) Architectures

In high-speed communication systems, multiplexers enable Time-Division Multiplexing (TDM), where multiple low-bandwidth signals share a single high-bandwidth channel. The multiplexer sequentially samples each input signal at intervals shorter than the Nyquist period, governed by:

$$ f_s \geq 2 \cdot \max(f_{i}) $$

where \( f_s \) is the sampling frequency and \( f_{i} \) are the input signal bandwidths. For a system with \( N \) channels, the aggregate data rate \( R \) becomes:

$$ R = \sum_{i=1}^{N} R_i \leq C_{\text{channel}} $$

where \( C_{\text{channel}} \) is the channel capacity derived from Shannon-Hartley theorem.

Wavelength-Division Multiplexing (WDM) Systems

Optical networks employ demultiplexers to separate wavelength channels in WDM systems. A diffraction grating or arrayed waveguide grating (AWG) resolves wavelengths \( \lambda_i \) according to:

$$ \Delta \lambda = \frac{\lambda^2}{n_e \cdot \Delta L} $$

where \( n_e \) is the effective refractive index and \( \Delta L \) is the path length difference. Modern DWDM systems achieve channel spacings of 0.4 nm in the C-band (1530–1565 nm).

Crossbar Switching in Telephony

Telephone exchanges historically used electromechanical multiplexers as crossbar switches. The non-blocking condition for an \( N \times N \) switch requires:

$$ \text{Crosspoints} \geq 2N - 1 $$

Modern digital switches implement this via Clos networks, reducing crosspoint complexity from \( O(N^2) \) to \( O(N^{1.5}) \).

Error Propagation Analysis

Multiplexer synchronization errors induce inter-channel interference. For a system with clock jitter \( \sigma_t \), the signal-to-noise ratio (SNR) degradation is:

$$ \text{SNR}_{\text{deg}} = 20 \log_{10}\left(\frac{\sigma_t}{T_s}\right) $$

where \( T_s \) is the symbol period. Advanced systems use elastic buffers and phase-locked loops to maintain \( \sigma_t < 0.1T_s \).

Case Study: SONET/SDH Framing

Synchronous Optical Networking (SONET) employs byte-interleaved multiplexing. The STS-1 frame structure (810 bytes) includes:

Higher rates (STS-n) concatenate \( n \) STS-1 frames, with pointer bytes handling clock drift up to ±8 ppm.

Line Overhead (27B) Payload (783B)
Use in Communication Systems in Multiplexers and Demultiplexers
Diagram Description: A diagram would show the sequential sampling process in TDM and the wavelength separation in WDM, which are highly visual concepts.

4.4 Role in Data Acquisition Systems

In high-channel-count data acquisition systems (DAQs), multiplexers and demultiplexers serve as critical components for routing analog or digital signals between sensors, ADCs, and processing units. Their primary function is to enable time-division multiplexing of multiple input channels onto a single ADC, drastically reducing system cost and complexity while maintaining sampling fidelity.

Channel Expansion and Signal Integrity

A typical N-channel DAQ system employs an analog multiplexer (MUX) with n select lines to sequentially connect 2n input channels to a shared ADC. The settling time (tsettle) of the MUX-ADC combination must satisfy:

$$ t_{settle} \leq \frac{1}{f_{sample} \cdot N_{channels}} - t_{conversion} $$

where fsample is the aggregate sampling rate and tconversion is the ADC's conversion time. High-speed DAQs often use pipelined multiplexing, where one channel settles while another converts.

Cross-Talk and Isolation Metrics

Channel-to-channel isolation is quantified by the off-state impedance (Zoff) and capacitive coupling (Cstray). For a 16-bit system, the required isolation between channels must satisfy:

$$ 20 \log_{10}\left(\frac{Z_{off}}{Z_{source} + Z_{on}}\right) > 96 \text{ dB} $$

Modern CMOS multiplexers achieve >100 dB isolation at 1 MHz through guard ring techniques and differential signaling.

Digital Demultiplexing in High-Speed DAQs

In time-interleaved ADC architectures, demultiplexers distribute the digitized output stream to parallel DSP units. The timing skew (Δt) between demux paths must be less than:

$$ \Delta t \leq \frac{0.5}{2^{ENOB} \cdot f_{Nyquist}} $$

where ENOB is the effective number of bits. Fiber-optic DAQ systems often employ WDM demultiplexers with <1 ps skew for terahertz-bandwidth applications.

Case Study: LHC Beam Monitoring

The Large Hadron Collider's beam loss monitoring system uses radiation-hard 256:1 multiplexers to acquire data from 100,000 sensors. The design employs:

This implementation demonstrates the trade-off between channel density (256:1) and fault tolerance (triple redundancy) in extreme environments.

Advanced Techniques

State-of-the-art systems implement adaptive multiplexing, where the channel sequencing dynamically prioritizes signals exhibiting rapid transients. The selection algorithm computes a priority metric Pi for each channel:

$$ P_i = \alpha \left|\frac{dy_i}{dt}\right| + \beta \left|y_i - \bar{y}\right| $$

where yi is the signal value and α, β are application-specific weights. This approach increases the effective bandwidth for sparse signals by 3-5× compared to round-robin sampling.

Role in Data Acquisition Systems in Multiplexers and Demultiplexers
Diagram Description: The section describes complex signal routing and timing relationships in DAQ systems that would benefit from visual representation of MUX-ADC interactions and timing constraints.

5. Recommended Books and Papers

5.1 Recommended Books and Papers

5.2 Online Resources and Tutorials

5.3 Research Articles and Case Studies