1.1 Definition and Basic Characteristics

Random Telegraph Noise (RTN) is a low-frequency noise phenomenon observed in semiconductor devices, particularly in nanoscale transistors, where the current or voltage signal exhibits discrete, step-like fluctuations between two or more metastable states. These transitions resemble the binary signal of a telegraph, hence the name. RTN arises from the capture and emission of charge carriers by individual defect sites, such as oxide traps or interface states, within the transistor's active region.

Physical Origin

The primary mechanism behind RTN involves the stochastic trapping and detrapping of charge carriers (electrons or holes) at defect sites near the semiconductor-oxide interface. When a carrier is captured by a trap, it alters the local electrostatic potential, modulating the channel conductance. The resulting fluctuation in drain current I_D or threshold voltage V_TH appears as a discrete switching event.

Here, g_m is the transconductance, θ represents the mobility degradation factor, and ΔV_TH is the threshold voltage shift due to a single trap.

Key Characteristics

• Amplitude: The magnitude of RTN fluctuations depends on trap location relative to the channel. Traps closer to the interface induce larger ΔI_D or ΔV_TH.
• Time Constants: The mean dwell times in high and low states (τ_c and τ_e) follow an Arrhenius dependence on temperature:

where E_a is the activation energy and τ₀ is the attempt-to-escape time.

• Spectral Density: The power spectral density (PSD) of RTN follows a Lorentzian distribution:

Measurement and Observation

RTN is typically measured in the time domain using high-resolution sampling of the drain current under constant bias conditions. Advanced techniques like time-lag correlation or wavelet analysis help distinguish RTN from other noise sources like 1/f noise. In modern nanoscale MOSFETs, RTN becomes more pronounced due to reduced channel dimensions and higher trap densities.

Practical Implications

In analog circuits, RTN introduces offset voltage drift in amplifiers and comparators. In digital systems, it causes timing jitter and bit errors in memory cells. The statistical nature of RTN makes it a critical reliability concern for sub-20nm technologies, where single-trap effects dominate device variability.

1.2 Historical Context and Discovery

The phenomenon now known as Random Telegraph Noise (RTN) was first observed in the late 1950s and early 1960s during the study of electronic conduction in semiconductors. Early reports described it as burst noise or popcorn noise due to its characteristic abrupt switching between discrete current levels, resembling the popping sound of popcorn. The first documented observations were made in germanium and silicon point-contact transistors, where researchers noticed anomalous fluctuations in collector current that could not be explained by conventional thermal or shot noise.

Early Observations and Theoretical Frameworks

In 1957, Bell Labs researchers McWhorter and Kingston reported discrete switching events in germanium transistors, attributing the behavior to trapping and detrapping of charge carriers at defect sites in the semiconductor bulk or surface states. This laid the foundation for the trapping-detrapping model, which remains central to RTN theory. The noise was found to follow a Lorentzian power spectral density (PSD) given by:

where A is the amplitude and f_c is the corner frequency, determined by the trap's characteristic time constants.

Advancements in the 1970s–1980s

With the advent of metal-oxide-semiconductor (MOS) technology, RTN became more pronounced due to the increasing influence of oxide traps. In 1975, Hsu and Walia demonstrated that RTN in MOSFETs was strongly correlated with oxide defects, particularly near the Si-SiO₂ interface. The development of deep-submicron transistors in the 1980s further highlighted RTN's impact on device reliability, as smaller geometries made individual traps more statistically significant.

Modern Understanding and Applications

Today, RTN is recognized as a critical reliability concern in nanoscale CMOS devices, where single charge traps can cause measurable threshold voltage shifts. Advanced characterization techniques, such as time-domain defect spectroscopy, now allow precise mapping of trap energy and spatial distributions. RTN is also leveraged as a probe for studying defect physics and as a stochastic signal source in emerging applications like hardware security and true random number generation.

Key Parameters: Amplitude and Time Constants

Random Telegraph Noise (RTN) in transistors is characterized by two fundamental parameters: the amplitude of the discrete switching events and the time constants governing their statistical behavior. These parameters are critical for understanding RTN's impact on device performance, particularly in nanoscale MOSFETs where single charge trapping dominates low-frequency noise.

Amplitude of RTN

The amplitude ΔI_D represents the discrete change in drain current when a charge carrier is trapped or released from a defect site. For a MOSFET operating in saturation, this can be expressed as:

where g_m is the transconductance, q the elementary charge, C_ox the oxide capacitance per unit area, and W, L the transistor dimensions. The amplitude follows an 1/(WL) scaling trend, making it increasingly significant in scaled technologies.

Capture and Emission Time Constants

The switching dynamics between trap states are described by:

where τ_c and τ_e are capture/emission time constants, σ the trap cross-section, v_th the thermal velocity, n the carrier concentration, and ΔE the activation energies. These time constants typically range from microseconds to seconds at room temperature.

Statistical Distribution

In real devices, multiple traps create a superposition of switching events. The power spectral density (PSD) of RTN exhibits Lorentzian characteristics:

where τ_i = (τ_c,i^-1 + τ_e,i^-1)^-1 is the effective time constant for the i-th trap. This results in 1/f noise when considering a uniform distribution of activation energies.

Measurement Techniques

• Time-domain analysis: Direct observation of discrete switching in ultra-low-noise measurement setups
• Noise spectroscopy: Extraction of individual Lorentzian components from PSD measurements
• Arrhenius plots: Temperature-dependent studies to determine activation energies

Advanced characterization methods like gate-controlled RTN analysis can spatially localize traps within the oxide by correlating amplitude variations with gate bias.

2.1 Charge Trapping and Emission Processes

Random Telegraph Noise (RTN) in transistors arises primarily from the capture and emission of charge carriers by defect states within the gate oxide or at the oxide-semiconductor interface. These defect states, often referred to as traps, act as temporary storage sites for electrons or holes, leading to discrete fluctuations in the drain current.

Physical Mechanism of Charge Trapping

When a bias voltage is applied to the transistor gate, charge carriers (electrons or holes) may tunnel into oxide traps near the semiconductor interface. The probability of capture depends on the trap's energy level relative to the Fermi level and its spatial location. The capture rate τ_c is given by:

where σ is the trap capture cross-section, v_th is the carrier thermal velocity, and n is the free carrier concentration. The emission rate τ_e follows an Arrhenius dependence:

Here, ν₀ is the attempt-to-escape frequency, E_T is the trap energy depth, k_B is Boltzmann's constant, and T is temperature.

Two-State RTN Model

A single trap generates a two-level RTN signal, where the drain current switches between high (I_high) and low (I_low) states. The time spent in each state follows an exponential distribution:

where t_c and t_e are the capture and emission times, respectively. The relative amplitudes of the current fluctuations depend on the trap's Coulombic influence on the channel potential.

Impact on Device Performance

In nanoscale transistors, RTN manifests as threshold voltage shifts (ΔV_th), which degrade analog circuit precision and digital logic reliability. For a trap located at a distance x from the interface, ΔV_th is approximated by:

where q is the elementary charge, C_ox is the oxide capacitance, and t_ox is the oxide thickness. Multiple traps produce superimposed RTN signals, complicating noise analysis in advanced nodes.

Measurement Techniques

Time-domain analysis of RTN requires high-resolution sampling (≥1 MS/s) to resolve fast transitions. Spectral techniques, such as noise power spectral density (PSD) measurements, reveal characteristic 1/f² roll-off at frequencies above (τ_c + τ_e)^-1:

Cryogenic measurements (T < 10 K) isolate individual traps by suppressing thermal emission processes, enabling precise trap spectroscopy.

2.2 Role of Defects and Interface States

Random Telegraph Noise (RTN) in transistors arises primarily from charge trapping and detrapping events at defect sites, particularly at the semiconductor-oxide interface or within the gate dielectric. These defects act as localized trapping centers, modulating the channel carrier density and mobility through Coulomb scattering or trapping-induced potential fluctuations.

Defect-Induced Carrier Trapping

The trapping and detrapping of carriers at oxide defects follow a Poisson process, where the time constants for capture (τ_c) and emission (τ_e) are governed by:

where σ is the capture cross-section, v_th the thermal velocity, n the free carrier density, N_c the effective density of states, and E_a the activation energy. The resulting current fluctuation amplitude ΔI_d in a MOSFET depends on the trap's location relative to the channel:

where x_t is the trap depth in the oxide, t_ox the oxide thickness, and L_eff the effective channel length.

Interface State Dynamics

Silicon dangling bonds (Pb centers) and oxygen vacancies at the Si/SiO₂ interface create energy states within the bandgap. These interface traps (D_it) contribute to RTN through:

• Border traps: Oxide defects near the interface that exchange carriers with the channel
• Switching oxide traps: Defects that alter their charge state based on Fermi level position
• Peroxide bridges: Metastable defects causing multi-level RTN signatures

The trap energy distribution follows an U-shaped profile across the bandgap, with higher densities near the conduction and valence band edges. Hydrogen passivation during fabrication can reduce D_it by several orders of magnitude.

Technology Scaling Effects

In nanoscale transistors, single defects cause larger relative current fluctuations due to:

High-κ dielectrics introduce additional defect types like oxygen vacancies (V_O²⁺) with higher activation energies (0.3-1.2 eV) compared to SiO₂ defects (0.1-0.5 eV). FinFETs and nanowire transistors show enhanced sensitivity to interface traps due to their 3D electrostatics.

Advanced characterization techniques like time-dependent defect spectroscopy (TDDS) map the spatial and energy distribution of traps, revealing clusters of defects near the source/drain extensions where hot carrier injection is prevalent.

2.3 Impact of Transistor Scaling on RTN

The relentless scaling of transistor dimensions in accordance with Moore's Law has profound implications for Random Telegraph Noise (RTN). As device geometries shrink below the 10 nm node, single charge trapping events induce larger relative fluctuations in drain current, exacerbating RTN effects. This section examines the scaling-dependent mechanisms governing RTN amplitude and time constants.

Dependence of RTN Amplitude on Device Area

The normalized drain current fluctuation caused by a single trap is given by:

where W and L are the transistor width and length, respectively, and μ_eff is the effective carrier mobility. The inverse proportionality to gate area (WL) means that scaling exacerbates RTN impact - a 10× reduction in linear dimensions yields a 100× increase in relative current fluctuation.

Voltage Dependence and Scaling Effects

In nanoscale MOSFETs, the gate voltage dependence of RTN follows:

where α ranges from 1.5 to 2.5 depending on device geometry. Threshold voltage (V_TH) scaling compounds this effect, as modern devices operate with smaller V_GS - V_TH overdrive voltages.

Interface Trap Scaling

The density of oxide traps (N_ot) per unit area remains relatively constant across technology nodes, meaning the absolute number of traps in a device scales with area:

However, the effective trap density per carrier increases dramatically due to reduced inversion charge (Q_inv) in scaled devices:

where t_ox is oxide thickness and E_ox is oxide field. This explains why RTN becomes more prominent in aggressively scaled technologies despite improved gate oxide quality.

Time Constant Distribution

The emission/capture time constants (τ_e, τ_c) in nanoscale transistors exhibit broader distributions due to:

• Increased lateral electric fields altering trap potential profiles
• Quantum confinement effects in ultra-thin bodies
• Statistical variability in dopant distributions

The time constant dispersion follows a log-normal distribution:

where μ and σ increase with scaling due to the above mechanisms.

Practical Implications for Circuit Design

These scaling effects manifest in several critical ways:

• SRAM stability: RTN-induced V_TH fluctuations exceed 50 mV in sub-20 nm nodes, requiring robust design margins
• Analog circuits: Increased 1/f noise corner frequencies demand new compensation techniques
• Memory devices: Trap-assisted leakage and retention time variations limit scaling of DRAM and flash

3.1 Time-Domain Analysis Methods

Time-domain analysis of Random Telegraph Noise (RTN) involves capturing and interpreting discrete switching events in the drain current or threshold voltage of a transistor. The primary objective is to extract statistical parameters such as capture and emission time constants ($${\tau }_c$$ and $${\tau }_e$$), amplitude distributions, and defect activation energies.

Direct Time-Domain Measurement

High-resolution oscilloscopes or specialized current amplifiers sample the drain current $$I_D$$ at nanosecond-scale intervals. The sampling rate must exceed the expected RTN switching frequency by at least a factor of 10 to avoid aliasing. For a defect with characteristic time constants $${\tau }_c$$ and $${\tau }_e$$, the minimum sampling frequency $$f_s$$ is given by:

Statistical Analysis of Switching Events

The dwell times in high and low current states follow exponential distributions. For $$N$$ observed transitions, the probability density function (PDF) for capture times is:

where $$⟨{\tau }_c⟩$$ is the mean capture time. Maximum likelihood estimation (MLE) provides optimal parameter extraction:

Correlation with Bias Conditions

The time constants exhibit strong dependence on gate voltage $$V_G$$ and temperature $$T$$. The emission time constant follows an Arrhenius relationship:

where $$E_A$$ is the activation energy and $${\tau }_0$$ the attempt frequency prefactor. In nanoscale MOSFETs, the gate voltage dependence often follows:

where $$\alpha$$ is the voltage sensitivity parameter, typically 0.5–5 V⁻¹.

Practical Implementation Challenges

• Bandwidth limitations: Oscilloscope noise floors must be below the RTN amplitude, typically 0.1–10 μV/√Hz for modern CMOS.
• Time resolution: Sub-microsecond transitions require sampling rates >100 MSa/s, complicating long-duration measurements.
• Multi-level RTN: Overlapping defects produce complex waveforms requiring advanced decomposition algorithms like Hidden Markov Models (HMMs).

Modern implementations use real-time triggering systems to capture intermittent events, with post-processing via wavelet transforms or Bayesian inference to separate overlapping defects.

3.2 Frequency-Domain Approaches

Random Telegraph Noise (RTN) in transistors exhibits discrete switching between two or more states, which manifests as Lorentzian-like spectra in the frequency domain. Unlike white noise, RTN has a distinct 1/f characteristic at low frequencies, making frequency-domain analysis essential for extracting trap parameters such as capture/emission time constants (τ_c, τ_e) and energy levels.

Power Spectral Density (PSD) of RTN

The PSD of a two-level RTN signal follows a Lorentzian distribution:

where ΔI is the current fluctuation amplitude, and f is the frequency. The corner frequency f_c is determined by the trap's time constants:

Extracting Trap Parameters

By fitting the measured PSD to the Lorentzian model, the following steps are taken:

• Identify corner frequency (f_c): The point where the PSD transitions from 1/f to 1/f² roll-off.
• Solve for time constants: If the duty cycle η = τ_c/(τ_c + τ_e) is known, τ_c and τ_e can be derived from f_c.
• Energy level estimation: Using the Arrhenius equation, the trap's activation energy E_T is found by measuring τ_c, τ_e at varying temperatures.

Practical Measurement Techniques

Frequency-domain analysis is typically performed using:

• Spectrum analyzers: Directly measure PSD up to GHz frequencies, but require high sensitivity for low-frequency RTN.
• Fast Fourier Transform (FFT): Applied to time-domain RTN data, though windowing artifacts must be mitigated.
• Cross-correlation methods: Reduce background noise by averaging multiple PSD measurements.

Challenges and Limitations

While frequency-domain methods are powerful, they face challenges:

• Multiple traps: Overlapping Lorentzians complicate parameter extraction, requiring advanced decomposition algorithms.
• Non-stationary noise: Drifting bias conditions or temperature can distort PSD measurements.
• High-frequency resolution: Accurate f_c determination demands long measurement times.

Case Study: Nanoscale MOSFETs

In sub-20nm MOSFETs, frequency-domain RTN analysis revealed traps near the Si/SiO₂ interface with time constants ranging from microseconds to milliseconds. Correlating PSD data with V_GS sweeps helped identify oxide defects contributing to threshold voltage instability.

where τ₀ is the attempt-to-escape period, and k_B is Boltzmann's constant.

3.3 Statistical Analysis of RTN Signals

Random Telegraph Noise (RTN) signals exhibit discrete switching between two or more discrete current or voltage levels, making them inherently stochastic. Statistical analysis is essential to characterize their behavior, extract trap parameters, and assess their impact on device reliability. Key statistical metrics include amplitude distribution, time constants, and correlation properties.

Amplitude Distribution and Probability Density Function

The amplitude of an RTN signal is typically bimodal, corresponding to the discrete states of a charge trap. The probability density function (PDF) of the signal can be modeled as a weighted sum of Gaussian distributions:

where N is the number of discrete states, w_i is the weight (occupation probability) of the i-th state, and μ_i and σ_i are the mean and standard deviation of the corresponding Gaussian component. For a two-level RTN signal (N = 2), the weights are determined by the ratio of dwell times in each state.

Extraction of Time Constants

The dwell times in each state follow an exponential distribution, reflecting the Poisson nature of charge trapping and detrapping events. The probability density of dwell times τ in a given state is:

where τ₀ is the mean dwell time, inversely related to the trap's emission or capture rate. Experimentally, τ₀ is extracted by fitting a histogram of measured dwell times to the exponential distribution. For multiple traps, the distribution becomes a sum of exponentials, complicating the analysis.

Autocorrelation and Power Spectral Density

The autocorrelation function (ACF) of an RTN signal provides insight into its temporal correlations. For a two-level RTN process, the ACF decays exponentially:

where σ² is the variance of the signal, and τ_c is the correlation time, given by the harmonic mean of the dwell times in the two states. The power spectral density (PSD) of the RTN signal, obtained via Fourier transform of the ACF, follows a Lorentzian shape:

This 1/f² behavior at high frequencies distinguishes RTN from 1/f noise, aiding in its identification in mixed noise environments.

Practical Implications for Device Characterization

Statistical analysis of RTN is critical for assessing device reliability, particularly in nanoscale transistors where single traps can dominate noise behavior. By quantifying trap parameters (e.g., activation energies, capture cross-sections), engineers can optimize fabrication processes to minimize RTN. Advanced techniques, such as time-domain spectroscopy and machine learning-based pattern recognition, are increasingly used to automate RTN analysis in high-volume testing.

4.1 Effects on Threshold Voltage Variability

Random Telegraph Noise (RTN) induces discrete fluctuations in the threshold voltage (V_th) of MOSFETs due to the trapping and detrapping of charge carriers at defect sites near the Si-SiO₂ interface. These fluctuations manifest as discrete shifts in V_th, directly impacting device reliability and performance in analog and digital circuits.

Mechanism of V_th Variability

The threshold voltage shift (ΔV_th) caused by a single trap can be modeled as:

where q is the electron charge, C_ox is the oxide capacitance, W and L are the transistor width and length, and x_T is the position-dependent coupling factor. For a trap located at a distance z from the interface, x_T is approximated by:

Here, λ is the attenuation length of the trap’s electrostatic influence, typically on the order of 1–2 nm for modern CMOS technologies.

Statistical Distribution of ΔV_th

In nanoscale transistors, multiple traps contribute to V_th variability. The total threshold voltage shift follows a statistical distribution dominated by the worst-case trap. The standard deviation σ_ΔVth scales as:

This inverse dependence on device area highlights the increasing susceptibility of scaled technologies to RTN-induced variability.

Practical Implications

• Analog Circuits: RTN degrades signal-to-noise ratio (SNR) in amplifiers and introduces offset errors in precision analog designs.
• Digital Circuits: Timing jitter and bit errors in SRAM cells arise from V_th fluctuations, limiting yield in advanced nodes.
• Reliability Testing: BTI (Bias Temperature Instability) and RTN are often correlated, requiring joint characterization for accurate lifetime prediction.

Case Study: SRAM Stability

In a 65 nm SRAM cell, RTN-induced ΔV_th of just 10 mV can reduce static noise margin (SNM) by 15%, increasing the bit error rate (BER) by an order of magnitude. This sensitivity necessitates guardbanding in memory design, directly affecting power and performance trade-offs.

4.2 Influence on Digital and Analog Circuits

Random Telegraph Noise (RTN) manifests as discrete switching between two or more current levels in transistors due to charge trapping/detrapping at defect sites. Its impact varies significantly between digital and analog circuits, necessitating distinct mitigation strategies.

Digital Circuit Implications

In digital systems, RTN primarily affects timing margins and bit error rates:

• Timing jitter: Threshold voltage fluctuations induce delay variations in logic gates. For an inverter with load capacitance C_L, the propagation delay shift is:

where ΔV_th is the RTN-induced threshold voltage shift and I_DS the drain current. In advanced nodes below 28nm, this can exceed 5% of clock periods.

• SRAM stability: RTN in memory cells reduces static noise margin. The worst-case read stability condition becomes:

Experimental data shows RTN can reduce SRAM yield by 15-20% in 16nm FinFET arrays.

Analog Circuit Sensitivity

Analog circuits exhibit fundamentally different vulnerability profiles:

• Low-noise amplifiers (LNAs): RTN modulates transconductance g_m, creating phase noise. The equivalent input-referred noise spectral density is:

where τ_avg is the average trap time constant. This 1/f² characteristic corrupts phase-sensitive measurements.

• Data converters: In pipeline ADCs, RTN causes code-dependent offset errors. The differential nonlinearity (DNL) for an N-bit converter becomes:

where k denotes the specific code transition. Measurements in 40nm CMOS show DNL degradation up to 0.8 LSB.

Mitigation Techniques

Circuit-level countermeasures must be tailored to application domains:

Device-level optimizations include high-κ gate dielectrics to reduce trap density and strained silicon channels to minimize defect interaction.

4.3 RTN in Advanced CMOS Technologies

Scaling Effects on RTN Magnitude

As CMOS technology scales below 20 nm, the relative impact of random telegraph noise (RTN) increases due to two primary factors: the reduction in transistor gate area and the decreasing number of active charge carriers. The normalized amplitude of threshold voltage fluctuations (ΔV_th/V_th) follows:

where W and L are the transistor width and length, and N is the channel carrier density. For a 7 nm FinFET with W = 10 nm and L = 7 nm, single-trap-induced ΔV_th can exceed 30 mV, compared to <5 mV in 45 nm nodes.

Interface Trap Dynamics in High-κ/Metal Gates

Modern CMOS technologies employ high-κ dielectrics (e.g., HfO₂) and metal gates to reduce leakage currents. However, these materials exhibit:

• Higher oxygen vacancy density (10¹² cm^-2 vs. SiO₂'s 10¹⁰ cm^-2)
• Multi-level trapping states due to d-orbital electron capture
• Temperature-dependent emission times following a stretched exponential law:

where β ranges from 0.3–0.7 for HfO₂ versus 0.9–1.0 for SiO₂.

Statistical Distribution in Nanoscale Devices

In arrays of identical transistors, RTN parameters follow extreme value statistics. The probability P of observing a trap with time constant τ in a device with N equivalent traps is:

Measurements on 14 nm FinFET SRAM cells show 5σ variations in RTN-induced read failures when N < 100 per device.

Mitigation Techniques

Advanced foundries employ three primary countermeasures:

• Post-fabrication laser annealing to reduce interface state density by 40–60%
• Strain engineering to shift trap energy levels outside the operating voltage window
• Adaptive body biasing that compensates for RTN in real-time using on-chip sensors

5.1 Device-Level Optimization Techniques

Gate Oxide Engineering

Random Telegraph Noise (RTN) in MOSFETs is strongly influenced by charge trapping at the Si-SiO₂ interface and within the gate oxide. Reducing defect density through high-quality oxide growth techniques, such as nitridation or plasma-enhanced atomic layer deposition (PE-ALD), can suppress trap-assisted tunneling. The noise power spectral density S_I(f) scales with the density of active traps N_T:

where ΔI is the current fluctuation amplitude and τ is the trap time constant. Advanced gate stacks with high-κ dielectrics (e.g., HfO₂) exhibit reduced low-frequency noise due to their thicker physical thickness at equivalent oxide thickness (EOT).

Channel Doping Profile Optimization

Non-uniform doping profiles can modulate the electric field near the interface, altering trap emission/capture rates. Retrograde or halo doping reduces lateral field variations, while ultra-shallow junctions minimize bulk traps. The trap activation energy E_A follows:

where τ₀ is the attempt-to-escape time. Implantation techniques like low-energy boron or carbon co-implantation can passivate defects.

Strain Engineering

Mechanical strain alters the band structure and trap energy levels. For pMOSFETs, compressive strain shifts the valence band, reducing hole trapping probability. The strain-induced change in trap energy ΔE_T is given by:

where Ξ is the deformation potential and ε is the strain tensor. Techniques like SiGe source/drain or stress liners are empirically shown to reduce RTN by 30–50%.

Geometry Scaling

RTN amplitude scales inversely with device area due to the number fluctuation model. For a transistor with width W and length L, the relative current noise follows:

where ΔV_T,i is the threshold voltage shift from the i-th trap. FinFETs and nanowires show superior noise immunity due to their 3D electrostatics and reduced percolation paths.

Advanced Architectures

Multi-gate devices (e.g., FinFETs, GAAFETs) mitigate RTN through volume inversion and reduced surface scattering. The corner effect in planar transistors is eliminated, lowering localized field peaks. Cryogenic operation further suppresses thermal emission, with noise scaling as:

where γ ≈ 1.5–2 and β ≈ 0.8–1.2 for typical CMOS processes.

5.2 Circuit-Level Compensation Methods

Random Telegraph Noise (RTN) manifests as discrete switching between two or more current levels in transistors due to charge trapping/detrapping at defect sites. Circuit-level mitigation techniques focus on minimizing its impact through architectural or feedback-based approaches rather than device-level optimization.

Differential Pair Cancellation

RTN is partially canceled in differential amplifier configurations due to common-mode rejection. For matched transistors M1 and M2, the differential output voltage V_out is:

where A_d and A_cm are differential and common-mode gains. RTN appears as a common-mode perturbation if traps are symmetrically distributed, though process variations limit perfect cancellation.

Correlated Double Sampling (CDS)

CDS eliminates low-frequency noise, including RTN, by sampling the signal twice: once during reset (V_reset) and once during measurement (V_signal). The output becomes:

This subtracts the RTN baseline, assuming the trap state remains constant between samples. CDS is widely used in CMOS image sensors and precision ADCs.

Chopper Stabilization

Modulating the signal to higher frequencies shifts RTN to out-of-band regions, where it is filtered. The input signal V_in is multiplied by a square wave c(t) before amplification:

After amplification, demodulation returns the signal to baseband while pushing RTN to odd harmonics of the chopping frequency.

Current Steering DACs for Bias Compensation

In current-mirror circuits, RTN-induced current fluctuations are compensated by dynamically adjusting bias voltages via a digital-to-analog converter (DAC). A feedback loop measures the output current and adjusts the DAC to stabilize the operating point.

Implementation Example

A 6-bit DAC with LSB = 100 nA can correct RTN-induced deviations up to 6.4 µA. The settling time must be faster than the RTN switching rate, typically requiring bandwidths >1 MHz.

Auto-Zeroing Amplifiers

Periodic calibration cycles sample the amplifier’s offset (including RTN) and store it on a capacitor. During operation, the stored offset is subtracted from the output. Key constraints include:

• Calibration frequency must exceed the RTN switching rate
• Capacitor leakage limits hold time
• Added noise from switching artifacts

Case Study: RTN in Op-amp Input Stages

In a 65 nm CMOS op-amp, RTN in the input pair caused 0.5 µV/√Hz noise at 1 Hz. Implementing chopping at 100 kHz reduced the noise to 50 nV/√Hz, with residual effects from charge injection during modulation.

5.3 Process and Material Improvements

Random Telegraph Noise (RTN) in transistors is strongly influenced by fabrication processes and material choices. As device scaling continues into the nanometer regime, minimizing RTN becomes critical for ensuring reliable operation in analog and digital circuits. This subsection discusses key process and material optimizations that mitigate RTN.

Gate Oxide Engineering

The gate oxide interface is a primary source of trap-induced RTN. Silicon dioxide (SiO₂) has been the traditional dielectric, but its thinning in scaled devices increases defect density. High-κ dielectrics such as HfO₂ and Al₂O₃ reduce direct tunneling while maintaining low trap densities. The relationship between oxide thickness (t_ox) and trap-induced RTN amplitude can be modeled as:

where ΔV_T is the threshold voltage shift, q is the electron charge, and C_ox is the oxide capacitance. High-κ materials allow thicker physical oxides with equivalent electrical thickness, reducing trap coupling.

6.1 Key Research Papers and Reviews

6.2 Books and Monographs on Noise in Semiconductors

6.3 Online Resources and Tutorials