AD8195 and DDC buffers

  
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The DDC lines on HDMI connector side are 47KOhms 5V PU and 2KOhms 3. 3V PU on FPGA side. Our schematic look like this one: This glitch is part of the normal operation of the DDC buffer in the AD8195. The glitch only occurs on the rising edge of the transmitting side of the DDC transaction and therefore should not adversely affect the receiving device.
AD8195 and DDC buffers - schematic

Perhaps there is another issue causing the read/write errors. I`ll be happy to help diagnose the issue. What is the source device What is SCL frequency Do failures occur during reads or writes or both Can you provide a view of the failing DDC transaction both on input and output of AD8195



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