Klee Sequencer Circuit Theory of Operation

Clock and Load functions, with Load being the first function described. U5, CD4013, performs the load function by controlling whether the shift register ICs are in the parallel or serial mode. For 99. 99% of the time, the shift registers are in the serial mode. In the serial mode, each shift register will cycle bits through the register, left to right. With each clock pulse, the
Klee Sequencer Circuit Theory of Operation - schematic

bit present on the serial input of the shift register will enter the shift register, and the bit present in the eighth position of the shift register will pass out of the shift register. In the parallel mode, each shift register will "look at" the bits programmed on its parallel inputs. The pattern switches set these bits. The switch to and from the parallel mode is a very fast operation - this mode looks at the bit pattern programmed by the pattern switches only long enough to load the data, then the shift registers revert back to serial mode. Two shift register control signals are generated by U5. When the PSA signal goes high, it puts the shift registers in the serial mode. Immediately afterwards, the R Async signal goes high. When R Async goes high, it clocks the parallel data into the shift registers on its rising edge. Nearly as soon as it goes high, R Async goes low, which in turn causes PSA to go low, which puts the shift registers back in serial mode. The CD4013 calls these shots, and it is told to do so by the rising edge of a pulse applied to the clock pin of its first stage (pin 3). There are three events that can produce this triggering event: The rising edge of the signal applied to U5, pin 3, clocks the first section`s Q signal (pin 1) high. This pulls the PSA signal high. When PSA is high, the two shift register ICs are put into the parallel mode. When PSA ("Q" pin 1 of U5) transitions from low to high, the...

Leave Comment

characters left:

New Circuits