Tug of War (Verilog)

Tug Of War is a game developed on an FPGA. The digital circuit was designed using Verilog and operates as a Finite State Machine (FSM).

The Tug Of War game implemented on an FPGA utilizes a Finite State Machine (FSM) architecture to control the game logic and state transitions. The FSM is designed to manage different states of the game, such as initializing, waiting for player input, processing game actions, and determining the winner.

In the FSM, each state corresponds to a specific phase of the game. For instance, the initial state may set up the game parameters and prepare the display for player interaction. The subsequent states handle player inputs, such as button presses or joystick movements, which are captured through the FPGA's input pins. The FSM processes these inputs to update the game state, which may involve changing scores, updating the game display, or transitioning to a win/lose state.

The design includes various combinational and sequential logic components. Combinational logic is used to determine the next state based on the current state and inputs, while sequential logic is responsible for maintaining the current state of the FSM. The Verilog code effectively describes these components, ensuring that the timing and sequencing of state transitions are synchronized with the clock signal provided by the FPGA.

Furthermore, the output of the FSM can interface with visual indicators, such as LEDs or a display module, to provide real-time feedback to players. Additional features may include sound effects or score tracking, which can be integrated into the design by expanding the FSM states and incorporating additional hardware components.

Overall, the Tug Of War game exemplifies the application of digital design principles, showcasing how an FSM can be utilized within an FPGA to create an interactive gaming experience.Tug Of War is a game that I made on an FPGA. The digital circuit was created using Verilog. It is a FSM (Finite State Machine). 🔗 External reference