low power universal demultiplexer decoder

This is a circuit for universal decoder that has functions as either a dual 1-of-4 decoder or as a single 1-of-8 decoder, depending on the signal applied to the Mode Control (M) input. Here`s the figure of the test circuit; In the dual mode, each half has a pair of active-LOW Enable (E) inputs. Pin assignments for the E inputs are such that in the
low power universal demultiplexer decoder - schematic

1-of-8 mode they can easily be tied together in pairs to provide two active-LOW enables (E1a to E1b, E2a to E2b). Signals applied to auxiliary inputs Ha, Hb and Hc determine whether the outputs are active HIGH or active LOW. In the dual 1-of-4 mode the Address inputs are A0a, A1a and A0b, A1b with A2a unused (i. e. , left open, tied to VEE or with LOW signal applied). In the 1-of-8 mode, the Address inputs are A0a, A1a, A2a with A0b and A1b LOW or open. All inputs have 50 kX pull down resistors. [Circuit diagram source: National Semiconductor Application Notes]

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