thermostat design

  
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We are planning to use a Programmable Logic Device to control our seven-segment displays. This will be accomplished by using the 8 outputs from the Analog to Digital converter as the inputs to the PLD, and by having the PLD generate 14 outputs to drive the 7 segments of each display. In our design, only 15 of the possible 256 intervals output from
thermostat design - schematic

the Analog to Digital converter will be used, each corresponding to a specific temperature in degrees. We plan to configure our PLD basically at first, and then refine the program once the rest of the circuit has been implemented. LIBRARY IEEE; USE IEEE. std_logic_1164. all; use IEEE. std_logic_unsigned. all; ENTITY jeff IS PORT(temperature : in std_logic_vector (7 downto 0); clk : in std_logic; display : out std_logic_vector (13 downto 0); END jeff; ARCHITECTURE interior of jeff is BEGIN PROCESS (clk) BEGIN if (rising_edge(clk) then case temperature is when "00000000" => display <= "10110111001111"; -23 when "00000101" => display <= "10110111011011"; -22 when "00001010" => display <= "10110110000110"; -21 when "00001111" => display <= "10110110111111"; -20 when "00010100" => display <= "00001101100111"; -19 when "00011001" => display <= "00001101111111"; -18 when "00011110" => display <= "00001100000111"; -17 when "00100100" => display <= "00001101111100"; -16 when "00101000" => display <= "00001101101101"; -15 when "00101101" => display <= "00001101100110"; -14 when "00110011" => display <= "00001101001111"; -13 when "00110111" => display <= "00001101011011"; -12 when "00111100" => display <= "00001100000110"; -11 when "01000001" => display <= "00001100111111"; -10 when "01000110" => display <= "01111111100111"; -09 when others => display <= "11110011111001"; -EE end case; end if; end PROCESS; END interior; In order to...



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