By inverter Gl, delay and width morning circuit 02 (CD4069) and RC integrating circuit configuration shown. When not gate output high when OI, C capacitor through Rl, D charge,
C voltage quickly filled to G2 input threshold level. When Gl output low, C through R2 to the output terminal Gl of low level discharge, due R2-10Rl, therefore, C discharge time is 10 times the charging time. Therefore, the output pulse is delayed while G2 is widened.