Hour time-delay sampling circuit

  
The circuit lowers the effective peak current of the output PUT, Q2. By allowing the capacitor to charge with high gate voltage and periodically lowering gate voltage, when Ql fires, the timing resistor can be a value which supplies a much lower current than IP. The triggering requirement here is that minimum charge to trigger flow through the timing resistor during the period of the Ql oscillator.
Hour time-delay sampling circuit  - schematic

This is not capacitor size dependent, only capacitor leakage and stability dependent.




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