The circuit monitors and displays a digital signal`s duty cycle and provides accuracy as high as ±1%. Using switch S2, you can choose a frequency range of either 250 Hz to 2. 5 kHz at ±1% accuracy or 2 kHz to 50 kHz at ±10% accuracy. The common-cathode display gives the signal`s duty-cycle percentage. Phase-locked loop re4 and counters Ie5A and re5B multiply the input frequency by a factor of either 10 or 100, depending on switch S2`s setting.
Duty-cycle-monitor - schematic

re6A and re6B count this multiplied frequency during the incoming signal"s mark interval. re7 and res then latch this count and display it at the clock"s sample rate. For example, ifyou select a 1 % resolution, when the signal"s mark periodis 40% of the total period, the circuit will enable the counter comprising re6A and re6B for 40 counts. To obtain space-interval sampling, you can reverse the input polarity using switch Sl. re2A samples the input signal"s period and enables gate reze and resets the counter. Ie2E and re2F form the sample-rate clock; re3B synchronizes the clock"s output with the input, so that the circuit can update latches re7 and res.

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