DS Protocol (Data transfer via handshake)

The DS protocol was designed to provide firmware-based bidirectional host-to-slave inter processor communications for situations in which no hardware solution is available and the host and/or the slave in incapable of tending the interface in real time. The only specialized hardware required is two bidirectional I/O ports on each chip (alternatively two input ports and two tri-statable output ports may be used). When read, DS slaves conforming to the interface protocol appear as byte-wide two locations -one register for temporary storage of incoming data and one location for instructions. Instructions and data are send one byte at a time with each byte preceded by a control bit, which when set, indicates and instructions.
DS Protocol (Data transfer via handshake) - schematic

A cleared control bit indicates the following byte is data to be held in the Incoming Data Register until a later instruction byte tells the slave what to do with the data byte. DS messages are sent 9 bits at a time as one byte preceded by a control bit that indicates whether the byte following is meant to be stored in the Incoming Data Register or sent to the Instruction Interpreter. In the flowcharts below, the control bit is located in the carry bit in both the sending and receiving routines. The flowcharts and code on this page were written with the Atmel AVR processors in mind, but should be easily ported to other processors. The communications routines were coded directly from these flow charts. At the start of a bit transfer, the sender puts the data bit on the data line. After the data line has been given a chance to settle, the sender pulls the attention line low for some period of time. Periodically, it releases the attention line, waits for the line to settle, then peeks at the line to see if it is being held low by the receiver. If the receiver is holding the line low, to indicate that it has received the data bit, the sender inverts the data line to acknowledge the receiver holding the attention line low. The receive, upon seeing the data line reverse, releases the attention line, and the sender, seeing the attention line being released, releases the data line. That process concludes on bit transfer. While...

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