A positive-going trigger pulse can be used to start the timing cycle with the circuit shown. In this design, trigger input pin 2 is biased to 6V (1/z Vvv) by divider Rl and R2. Control input pin 5 is biased to 8 V (213 Vvvl by the internal divider circuit. With no trigger voltage applied, point A is at 4 V (1/3 Vvv). To tum the timer on, the voltage at point A has to be greater than the 6 V present on pin 2. Positive 5-V trigger pulse V, applied to the control input pin 5 is ac coupled through capacitor Cl, adding the trigger voltage to the 8 V already on pin 5; this results in 13 V with respect to ground.
Positive-triggered-monostable - schematic

The output pulse width is determined by the values of R, and C,. When voltage at point A is increased to 6.5 V, which is greater than the 6 V on pin 2, the timer cycle is initialized. The output of timer pin 3 increases, turning off discharge transistor pin 7 and allowing C, to charge through resistor R,. When capacitor C, charges to the upper threshold voltage of 8 V (2/3 Vvv), the flip-flop is reset and output pin 3 decreases. Capacitor C, then discharges through the discharge transistor. The timer is not triggered again until another trigger pulse is applied to contrgl input pin 5.

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