Posted on Feb 27, 2013

This circuit traps a single positive pulse from a square-wave train. Following the rising edge of an input command, the pulse-out signal emits a replica of one positive pulse of the clock signal simultane ous with the clock signal`s next rising edge. The 0 input command signal sets the Ql output of flip-flop `----IClA.

Click here to download the full size of the above Circuit.

Consequently, the next rising edge of the clock signal sets the Q2 output of IClB, which allows AND gate IC2C to pass the clock signal"s next positive pulse. AND gates IC2A and IC2B prevent the generation of brief output glitches by delaying the clock signal by tv seconds (two propagation delays).

Leave Comment

characters left:

New Circuits



Popular Circuits

RS232 cable modem
Remote on-off switch
DIY Infrared Sensor Module using Arduino
Circuit for controlling 8 appliances using TV Remote
class audio amplifiers
diac controlled led flasher
garageshed alarm
The PCS Scenemaster
A long-wave SWR meter
Boosters Are Not Buffers
Second-order active band stop filter circuit