Digital CMOS Circuits Tutorial

  

 

At this page (1) Page 2 Page 3 Page 4
⚛ Introduction To CMOS Technology ⚛ Logic CMOS Gates ⚛ Schmitt Trigger CMOS Circuit ⚛ Logic CMOS Families
⚛ The MOSFET Transistor ⚛ Static Logic CMOS Structures ⚛ Inputs Compatible with TTL levels ⚛ Conventional Logic CMOS Families
⚛ Operation of MOSFET Transistor ⚛ Dynamic CMOS Logic Structures ⚛ CMOS Output Levels ⚛ Low Voltage CMOS Logic Families
⚛ The MOSFET Transistor as a Switch ⚛ Alternative Logic Structures ⚛ CMOS Driving Capability ⚛ Inputs Tolerant to Overvoltages
⚛ Basic Structures of MOSFET Transistor ⚛ Input-Output CMOS Circuits ⚛ Other CMOS Output Structures ⚛ Evolution of CMOS Technology
⚛ MOSFET Propagation Gate ⚛ CMOS input levels ⚛ Power Consumption of CMOS Circuits  
⚛ Pull Up and Pull Down in CMOS ⚛ Non-Driven Inputs and Slow Transition Inputs ⚛ Static Power Consumption  
⚛ The CMOS Inverter   ⚛ Dynamic Power Consumption  
    ⚛ Charging of External Capacities  
    ⚛ Charging of Internal Capacities  
    ⚛ Short-Circuit Current  
    ⚛ Total Power Consumption  
    ⚛ Maximum Power Consumption  

 

 

 

Introduction To CMOS Technology

Modern digital circuits (logic gates, memories, processors and other composite circuits) are currently being implemented with a complementary metal-oxide semiconductor (CMOS) technology (> 75% of all digital circuits). This technology combines complementary p-type (pMOS) and n-type (nMOS) metal-oxide semiconductor field effect transistors (MOSFETs) for the construction of various logic circuits.

CMOS technology was developed later than that of bipolar transistors. In the early years of its commercial application (1970s) it was an alternative to low power systems due to the particularly low energy consumption of logic circuits with bipolar transistors. On the other hand, the main disadvantage of CMOS circuits was their slow operation.

In the next decades ('80 -'90), both CMOS technology and bipolar technology followed the manufacturing tendency to shrink transistor dimensions and increase operating speeds. Bipolar technology has remained faster, but has not achieved a significant reduction in power consumption. CMOS technology, however, was ideal for logic circuits of great integration and low power consumption.

In the early 1990s, the construction dimensions of the integrated circuits reached 0.5μm. This allowed the construction of very large CMOS circuits, the performance of which at system level exceeded the individual efficiency of the bipolar transistors. Since then, CMOS technology has been dominant in the field of digital circuits.

In this chapter, a brief review of the operation of the MOS transistor is first made and the features that allow for the implementation of digital circuits are described later. The structural element of CMOS technology is described below: the static inverter, which consists of a complementary pair of MOS transistors (pMOS and nMOS). Immediately thereafter, static and dynamic logic circuits are presented too and the tutorial concludes with the description of various logic CMOS families.

 

 

The MOSFET Transistor

The MOSFET transistor is the basis of CMOS logic technology. This transistor is a field effect transistor (FET): the conductivity of a channel between two terminals, a source and a drain, is controlled by the voltage applied to a third terminal, the gate. Unlike bipolar transistors, the gate does not leaking from current.

Figure 3-1 (a) illustrates the simplified structure of a MOSFET transistor (a real transistor may be structured in a different way). As shown in the figure, the gate is isolated from the channel area through a layer of SiO2. On the first transistors of this type the gate was made of metal, so the metal-oxide semiconductor FETs (MOSFETs). Today the gate is made of polycrystalline silicon (poly).

MOSFET Transistor (NMOS and PMOS)

 

Figure 3-1 

 

MOSFET transistors are manufactured in two formats, NMOS and PMOS, depending on the type of source and drain silicon (n-type and p-type, respectively). Figure 3-1 (a) depicts an NMOS transistor and Figure 3-1 (b) a PMOS transistor.

Figure 3-1 (c) shows the top view of a MOSFET, which shows the dimensions (L and W) of the channel below the gate. These dimensions are defined by the designer and are critical for the transistor's operating characteristics, such as the conductivity and gate capacities.

Each MOSFET transistor has a fourth terminal, substrate or body, in which the channel is formed between a source and a drain below the gate.

Under normal conditions, bipolar contact between the substrate and the source/drain (p-n for NMOS and n-p for PMOS) should be inversely polarized. Thus, in the NMOS transistor, the substrate is always connected to the negative supply voltage (ground), while the PMOS is connected to the most positive (VDD).

In the MOSFET transistors, which are used to construct logic circuits, the source and drain have no physical difference between them. By convention, in NMOS the source is negative than the drain (in voltage), while in PMOS the source is more positive.

MOSFET transistor symbols

 

Figure 3-2

 

Figure 3-2 shows the symbols of the NMOS and PMOS transistors both with and without the body terminal. The NMOS transistor requires a positive voltage at its gate to conduct, while the PMOS a negative, as indicated by the inversion cycle in the simplified PMOS symbol of Figure 3-2.

The previously presented transistors belong to the enhancement type, where the conductive channel is formed by the effect of voltage on the transistor gate. There is also a depletion MOSFET, where the conductive channel pre-exists and is interrupted by the influence of the gate voltage.

 

 

Operation of MOSFET Transistor

In a NMOS (PMOS) transistor, when a positive (negative) voltage at the gate is applied (to the source), a positive (negative) load accumulation is observed in the substrate area under the gate. When the voltage of the VGS source port exceeds a critical value, called the threshold voltage VT of the transistor, the area under the gate is "inverted" by p-type (n-type) to n-type (p-type). This inversion forms the conductive channel between source and drain.

The threshold voltage of a MOSFET transistor depends on the construction characteristics of the transistor and the VSB potential difference between the source and the substrate. The effect of VSB is called body effect and tends to increase the threshold voltage as VSB grows. The threshold voltage also depends on the temperature: as this increases, both the VT decreases (a decrease of about 1.5mV/°C).

Under normal circumstances, the threshold voltage of an NMOS transistor used in digital circuits has typical values ​​from 0.5V to 0.7V (the same applies to PMOS, except VT is negative).

The following table 3-1 summarizes the operating areas of a MOSFET transistor. The description is limited to the key points only, which will be used in subsequent sections to describe the operation of CMOS logic circuits. The description is completed with Figure 3-3, showing the characteristic current-voltage curves for a 0.35μm NMOS transistor.

The symbols used in Table 3-1 and Figure 3-3 are as follows:

  • IDS: drain-source current leaking through the transistor.
  • VGS: gate-source voltage
  • VDS: source-drain voltage.
  • VT: Threshold for the transistor.

It should be noted that the above voltages are positive for an NMOS transistor and negative for a PMOS, while the IDS current is opposite for the PMOS.

 

operating area

Conditions

Function for NMOS

(In brackets for the PMOS)

commentary

Cutoff region

for NMOS: VGS < VT 

 

the PMOS: VGS > VT

As the voltage VGS is less (greater) than the threshold voltage VT the current IDS is practically zero.

IDS = 0

The transistors may be regarded as substantially open circuit.

In fact there is a minimum current IDSwhich however is negligible (on the order of pA).

Resistive region

for NMOS: VGS ≥ VT

and

VDS <(VGS -VT )

 

the PMOS: VGS ≤ VT

and

VDS > (VGS -VT )

When the voltage VGS is greater (smaller) than the threshold voltage VT and the voltage VDS less (greater) than the value VGS-VT , then the current IDS is equal to:

IDS = k [ ( VGS -VT ) VDS + V2DS / 2 ]

The factor k is called gain factor and equals: k=μCOX(W/L), where μ is the mobility of charge carriers (electrons for NMOS and holes for the PMOS), COX is the capacity of oxide of the gate and W/L the dimensions of the gate.

The transistor acts as variable resistor, controlled by the voltage of the gate:

a) The current IDS is proportional to VGS.

b) The current IDS is also proportional to VDS.

For small values of VDS, the ratio is linear (A figure 3-3). For larger VDS overrides the condition of V2DS and the current IDS is changing nonlinearly (B in Figure 3-3)

Saturation region

for NMOS: VGS ≥ VT

and

VDS ≥ ( VGS -VT )

 

for PMOS: VGS ≤ VT

and

VDS ≤ ( VGS - VT )

When the voltage VDS is greater (smaller) than the value VGS -VT, then the channel load go away from the drain. The channel between source and drain decreases (pinch off) and the current IDS is equal to:

IDS = k ( VGS - VT )2 /2

The transistor acts as current source, controlled by the voltage of the gate:

a) The current IDS is proportional to V2GS.

b) The current IDS does not greatly depend on the VDS.

Theoretically the current IDS is independent of VDS. But n practice, much of the small dimensions transistors that are being used in digital logic circuits, the current IDS in the saturation region depends from the VDS (C in Figure 3-3). Also the IDS tends to depend on VGS and not by V2GS in this region.

 

 

Table 3-1

 

As can be seen from the "Comments" column of Table 3-1, the operation of the MOSFET transistor deviates from the theoretical model due to phenomena such as channel length modulation and velocity saturation of load carriers . But these phenomena will not be considered here.

The effect of the temperature on the operating parameters of the transistor is also significant: by increasing the temperature a) decreasing the threshold voltage; b) increasing the leakage current at the cut-off area; and c) reducing the mobility of the load carriers, transistor.

Typical I V curves of NMOS transistor

 

Figure 3-3

 

The PMOS transistor operates in exactly the same way as the NMOS and the characteristic curves of the voltage-current are similar to the difference being negative. In addition, the IDS current flowing through a PMOS transistor is smaller than the current of an NMOS of its own dimensions, because the charge carriers in the PMOS have lower mobility than the NMOS electrons by 1/3 to 1/2.

 

 

The MOSFET Transistor as a Switch

When analyzing CMOS digital circuits, the MOSFET transistor can be considered as a switch (Figure 3-4). Although this analysis seems super simplified, it satisfactorily approaches the behavior of the transistor because the two logic levels ("0" and "1") are at both ends of the power supply range (VDD and GND).

The MOS transistor as a switch

Figure 3-4

 

A NMOS transistor is in the cut state when its gate has a low logic level, while it is in the resistance range when a high level is applied to the gate (the opposite is true for PMOS). The equivalent resistance of the transistor in this region is denoted by RON and its value varies dynamically depending on the VDS voltage. RON is usually given as the mean value and for the typical transistors of a logic circuit (not for output transistors with increased power supply).. is in the order of kΩ.

When switching from one logic state to another, the transistors of a digital circuit are momentarily in the saturation region. In this area, a slight change in VGS gate voltage causes a large change in the IDS current, helping the logic circuit to change rapidly.

Parasitic Capacities

 

Figure 3-5

 

The operating speed of the MOSFET transistor as a "switch" is determined by the parasitic capacities formed between its various parts (Figure 3-5). These capacities cause current flow during charging and discharging and determine propagation delay of logic signals. The most important parasitic capacitance is that formed between the gate and the remaining parts of the transistor, which determines the charge required to move from / to the gate to change the state of the "switch". The capacity of the gate changes dynamically depending on the operating range of the transistor. The capacities between the drain or source and the substrate are of smaller size and importance.

 

 

Basic Structures of MOSFET Transistor

MOSFET transistors (NMOS and PMOS) are used in some basic arrangements for implementing complex logic functions. Two of these devices, the transmission / pass gates and the pullup / pulldown devices, are described below.

 

 

MOSFET Gate Propagation

A MOSFET transistor is used as a propagation gate to control the transmission of a logic level between the source terminals and the drain depending on the voltage applied to the transistor gate.

The NMOS transistor allows the signal to propagate when a high logic level (VDD) is applied to its gate while it is at the cut-off when its gate is connected to the low level (GND). The reverse is true for the PMOS transistor. However, the two types of transistors can not carry the low and high levels efficiently (without degrading the logic level).

MOSFET propagation gate

 

Figure 3-6

 

In figure 3-6, two transistors (NMOS and PMOS) are depicted at the low logic level propagation from their input to the output, which is connected to a CL load. Initially, the input and output are at a high logic level, while the gates of the two transistors apply the appropriate voltage so that they can be driven. When the input level is low, the CL is discharged via the transistors and the output gradually decreases. For NMOS, the VGS voltage is always higher than the VT, so the transistor runs continuously by discharging the CL until the output reaches the low logic level. However, this is not the case for PMOS, where the (negative) voltage VGS increases and sometime exceeds the (negative) VT of the PMOS, causing the transistor to stop before the output reaches the final low level. From the diagram of Figure 3-6 it is clear that PMOS can not transmit the low logic level.

CMOS propagation gate

 

Figure 3-7

 

The inverse applies to the propagation of the high logic level, where the NMOS transistor this time fails to transmit the fully high logic VDD level. For full propagation of both high and low levels, a PMOS and a NMOS transistor can be connected together, with their gates being driven by the supplementary control signal (Figure 3-7). This combination of complementary properties of the NMOS and PMOS transistors is the basis of CMOS (Complementary MOS) technology, as will be seen later on.

 

 

Pull Up and Pull Down in CMOS

The MOSFET transistor can be used as an active element for pull-up or pull-down the voltage of a node by connecting the node to the VDD or GND respectively, under voltage control applied to the gate of the transistor.

Pull-up feature

 

Figure 3-8

 

In analogy with the propagation gate, which was previously shown, the NMOS transistor can lead a node to a strong low level (GND) but produces a weak high level (less than VDD-VT). Conversely, the PMOS transistor produces a strong high logic level (VDD) but a weak low level (greater than VT). Figure 3-8 shows the final level of a CL load when driven to VDD (2.5V) by an NMOS and a PMOS transistor.

Using a NMOS transistor to pull-down the voltage and a PMOS to pull-up, we form a CMOS inverter, which is the building block of the CMOS technology which is discussed below.

 

 

The CMOS Inverter

Figure 3-9 illustrates the CMOS inverter, which is the basis for the implementation of CMOS logic circuits. The operating characteristics of the inverter can determine the function of all CMOS complex circuits.

The inverter consists of two MOSFET transistors: one PMOS and one NMOS. The VIN input is connected to the gates of the two transistors, while the VOUT output is connected to their drains. The source of the NMOS is connected to the ground (GND) and the PMOS to the VDD. It is recalled that the PMOS substrate is connected to the VDD, while the NMOS on the ground.

Inverter CMOS

 

Figure 3-9

 

The function of the inverter is generally the following: when the VIN input is at a low logic level (GND), the NMOS is cut off while the PMOS is running by connecting the VOUT to the high level (VDD). Conversely, when the input is at a high level, the PMOS is cut off and the NMOS conducts, thus connecting the output to the ground.

Figure 3-9 shows that:

  • A) VGS(NMOS) = VIN and VDS(NMOS) = VOUT
  •  
  • B) VGS(PMOS) = VIN - VDD and VDS(PMOS) = VOUT - VDD(negative values)
  •  

In Figure 3-10, the characteristic transfer curve (the VOUT output voltage to the VIN input voltage) of a CMOS inverter with VDD = 2.5V, VT(NMOS) = 0.5V and VT(PMOS) = - 0.5V . The same figure shows the VGS and VDS voltages for the two transistors (same curves in different scales for NMOS and PMOS).

CMOS Inverter Typical transfer curve

 

Figure 3-10

 

Initially, the VIN voltage is zero and the NMOS transistor is cut off, while the PMOS is in the resistance range. The VOUT output is connected to the VDD via the RON resistance of the PMOS. As the input voltage exceeds the threshold voltage of the NMOS, this goes into the saturation range and the output voltage as a combination of the currents of the two transistors begins to drop.

Then, for a very short time, the two transistors are in saturation. The output voltage changes sharply by approaching the low logic level. The point where VIN = VOUT is called Inverter Threshold (VINV). The VINV threshold voltage depends on the driving capability (power supply) of the two transistors and is given by:

 

VINV =  [ VT(NMOS) + [( kPMOS /  kNMOS )] (VDD + VT(PMOS)] / [...1 + [( kPMOS /  kNMOS )]]

 

With a stronger PMOS VINV increases, while with stronger NMOS VINV decreases. The ratio of the driving capability of the transistors is determined by their dimensions (L and W). To achieve symmetric driving capability and VINV equal to VDD / 2, the PMOS is 2 to 3 times larger than the NMOS. An inverter with symmetrical transition characteristics achieves similar transition times between the two logic levels and has the maximum noise margins.

As shown in Figure 3-10, the area where both transistors are at saturation is very narrow. The further increase in input voltage soon leads to NMOS in the resistance region. Completing the output transition from high to low logic level, PMOS passes to the cut-off area, leaving the output connected via NMOS to the low logic level.

Short circuit current (ISC)

 

Figure 3-11

 

An important feature of the CMOS inverter is the sort-circuit or cross-over current (ISC) that flows from the VDD to the ground at the moment of transition from one logic state to the other (Figure 3-11). The ISC current is due to the two transistors running simultaneously for a short time.

The peak of the ISC current is in the middle of the transition and is determined by the saturation current of the two transistors, therefore it is proportional to their magnitude. The ISC current is also proportional to the VDD power supply, and also depends on the VIN change rate relative to the VOUT switching speed (if the input changes faster than the output - eg if a large Capacitive load is connected at the output, then the time at which the transistors are running at the same time is shorter).

 

 

Continue to page 2