The schematic is shown above, and two switches S1 and S2 are used to control the outputs. The main work is done by U2 a CMOS4017 decade counter divider IC. At switch on, C1 is quickly charged by R4 and a brief reset pulse is applied to to the reset pins of both U1 and U2. This results in U1, a 7 segment display display driver and decade counter sh
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owing "zero" on the 7 segment display and pin 3 (which is the output zero) of the 4017 becoming high. Each time S1 is pressed the clock input of U2 is incremented, by one count and the display and 4017 will cycle through all 10 outputs. A separate reset switch is not provided as the display reads the currently selected output. Each output can be toggled (set or reset) independently by the use of a JK flip flop, a CMOS4027. When the 4017 is on a particular output, for example zero, then the controlled circuit can be turned on or off using switch S2. To latch the output a type JK flip-flop is used at each of the ten outputs. The 4027 contains two JK flip flops, and only one flip flop is required per output. If you only required 5 outputs, then only three 4027 IC`s are required. Three 4027 would give you six JK flip flops, the unused flip flop should have all unused inputs tied to ground. The circuit works as follows. When the 4017 is at output zero, pin 3 will be high. This enables both JK inputs of the flip flop (U4A at output zero) and the circuit can then be toggled via pulses applied from switch S2. The `Q` output of each flip-flop drives and NPN transistor and then a small relay. The NPN transistors can be any general purpose type, e. g. 2N2222, BC108, BC548 etc. The relay allows external loads of different voltage and current to this circuit to be controlled. Please note that VDD and VSS represent the drain and source...
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