This is a `beta release` schematic. Use at your own risk The idea is to add this circuitry to a board with already has ram at 2000 and an 82C55 I/O chip to provide ports A, B and C. Warning: not shown here is a memory mapping trick which is described below. You must figure out a way to provide the necessary memory mapping to make beta version 0. 00
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3 work. The next beta release will fix this problem, so that an ordinary memory configuration will work. but for now a hardware trick or some preprocessing of your intel hex files is needed. The AND and NAND gates shown should be 74HC08 and 74HC00 respectively. It a TTL type NAND gate is used (eg LS, L, S, ALS, etc) the crystal oscillator may be problematic. NOTE: in the above schematic, the line indicated P3. 3 (which controls the TXD echo feature) should really connect to P3. 4, and the one labeled P3. 4 really ought to connect to P3. 3. Sorry. I`ll get a fixed copy of this schematic on-line sometime, with the signals names that now appear in BETA Version 0. 004. On the bright side, if you do connect it differently, it`s a simple matter to reassign the pins in the software with 0. 004. The inputs on the left side of the schematic come from the ports on the 8051 and 82C55. Port A, Port B, and PC. 0 come from the 82C55, and the other lines are from the 8051. The TXD pin of the 8051 is connected to the TXD(in) input line, and the TXD(out) line is connected to the line driver for the programmer`s serial transmit. This simple three gate circuit provides the "echo-through" feature which is useful for troubleshooting code while the 89C2051 is in-circuit by echoing data to the programmer`s transmit line. The three NMOS transistors are within a single CD4007 chip. The trick here is to not use the three PMOS transistors which also...
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