Digital Compass Module HMC6352

Posted on Feb 5, 2014

From Figure 1, the host microprocessor (uP) controls the HMC6352 via I2C serial data interface lines for data (SDA) and clock (SCL). Two external 10k-ohm pull-up resistors to the nominal 3 volt DC supply create normally high logic states when the interface lines are not in use. The host initiates use of the interface by creating the 100kHz clock a

Digital Compass Module HMC6352
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nd pulling low the data line to indicate the start condition. The data line logic state transitions are only allowed during the clock low states and require the data line to be stable in the high states, with the exception of the start and stop conditions. The 0. 01uF supply decoupling capacitor in this reference can be omitted if another supply filter capacitor is already included in the overall circuit design. If the supply traces extend beyond a couple inches to the HMC6352, it is advisable to add a local supply decoupling capacitor near the HMC6352 to retain optimum circuit stability. Additional masters and slaves can be added to the I2C bus traces without interface trouble to the HMC6352. There are no periodic maintenance commands required, and even HMC6352 sleep mode or power shutdown can be accomplished without harm to the data or clock lines.

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