Mark 2 Memory circuit

Posted on Feb 6, 2014

The memory part of my Mark 2 system is extremely simple. There are two 32K SRAM chips (actually FRAM because I had them lying around, but there isn`t any significant difference in this application). These are selected with the logical OR of the MREQ signal and A15 (or inverse of A15 for the upper chip). Because the boot code for the Z80 is held by

Mark 2 Memory circuit
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the PIC and the PIC can control the whole address bus while it holds the Z80 in reset the boot code is written to normal RAM after power-on. This provides the advantage of less decode logic, and no ROM chip, as well as allowing the whole of the memory space to be used by whatever application is running as there are no "unwriteable" regions. The actual logic I used to generate the select signals is not OR gates, as there were none of these on the board, but NAND and NOT gates as I had spare of these from various other functions. The translation is based on De Morgan`s Laws about equivalence of inverted operators. Basically if I invert both inputs and output of an and gate it becomes an or gate. However since I have a NAND gate the output is already inverted, so inverting the inputs will make the output equivalent to my OR gate truth table. This actually only requires one extra gate as I would have to invert A15 anyway, the inverted version is just used in the select for the other chip now, and the extra gate is a NOT gate on the MREQ signal. I`ve mentioned here that I`m using FRAM chips. I currently don`t plan to use them for storage of data however, as I have found them somewhat "temperamental" in home made circuits in the past. If you are interested in storing data in them through power-cycles, it`s worth noting that somewhere in the data sheet it suggests using a pull-up resistor on the chip select pin, this avoids any...

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