Posted on Nov 21, 2012

The analog input is fed into the span resistor of a DAC. The analog input voltage range is selectable in the same way as the output voltage range of the DAC. The net current flow through the ladder termination resistance; i.e., 2 KO for HI-562A; produces an error voltage at the DAC output. This error voltage is compared with 1/z LSB by a comparator. When the error voltage is within ±1/z LSB range, the Q output of the comparators are both low, which stops the counter and gives a data ready signal to indicate that the digital output is correct.

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Ifthe error exceeds the ±1/z LSB range, the counter is enabled and driven in an up or down direction depending on the polarity of the error voltage. The digital output changes state only when there is a significant change in the analog input. When monitoring a slowly varying input, it is necessary to read the digital output only after a change has taken place. The data ready signal could be used to trigger a flip-flop to indicate the condition and reset it after readout. The main disadvantage of the tracking ADC is the time reqnired to initially acquire a signal; for a 12-bit ADC, it could be up to 4096 clock periods. The input signal usually must be filtered so that its rate of change does not exceed the tracking range of the ADC-1 LSB per clock period.

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