dual slope sampling SE

If time was spent experimenting with the ALF type SE circuit, some shortcomings related to a Power Smart Head adaptation may have been discovered. The issue arises because HCMOS gates consume significant power when utilized as SE voltage comparators, especially when the analog input voltage approaches the CMOS switching threshold. When an HCMOS gate is employed without sampling, the chip supply current can reach as high as 70mA when the comparator input voltage is near the trigger threshold (Vcc / 2). By sampling the analog input voltage, which indicates the level of Vcc, with narrow pulses, the power supply current can be reduced by the on/off ratio of the sampling pulse width. In the ALF circuit, the worst-case average current during a sampling period, with a comparator input voltage close to the threshold, is decreased to less than 100µA, although peak currents may still be in the 50mA range. Once the ALF circuit is triggered, the rest of the circuit controlled by the SE becomes active. During this active period, the main storage capacitor is rapidly discharged through the load for a duration significantly shorter than the charging time. This is crucial since the same high chip supply current caused by analog voltages at the comparator input during charging also occurs during the discharge period. For circuits like the Power Smart Head, which has a low power standby mode when locked onto balanced light, the discharge time can extend considerably. In standby mode, the total circuit supply current may be less than 1mA, allowing the charge on the main capacitor to last for many tens of minutes, if not for the inefficient method used to compare the reset voltage level. During discharge, the analog comparator input voltage is not sampled, causing the chip current to rise rapidly and prematurely discharge the storage capacitor. The dual slope sampling SE is the first of its kind, sampling the voltage comparator input during both charging and discharging. If the Power Smart Head is in standby, the storage capacitor is likely to remain fully charged, provided the <1mA supply current is available from the solar cell. The DS SE employs a similar number of components for the SE section as the ALF circuit, but its performance is enhanced in several ways. A bicore circuit is utilized for the oscillator to set the sample period and pulse width. This grounded bicore can control the pulse duty cycle by switching the reference voltage to the timing resistors from positive to Vcc, altering the pulse output from positive to negative pulses. The comparator employs a transistor front end to amplify the 1.2V reference voltage. The latch and oscillator outputs are connected through 200K resistors, with a summed sampling voltage applied to the diode and transistor base-emitter junction. The two resistors create a divide-by-two circuit, establishing a trigger level of approximately 2 x 1.2V = 2.4V and a trigger level of 2.1V, which is 300mV lower. Other resistor ratios can yield different trigger and reset voltages. During charging, the sampling circuit analog output voltage applied to the left-hand comparator inverter input is primarily near 0V, but the circuit generates narrow pulses approaching Vcc / 2 when the trigger level is reached. Conversely, during discharging, the sampling circuit output voltage applied to the left-hand comparator inverter input is mainly near Vcc, and the circuit generates narrow pulses approaching Vcc / 2 when the reset level is reached. The maximum supply current during charging is <60µA, and when triggered, the standby current is <100µA. With the specified component values, the trigger level is 2.5V, and the reset voltage is 2.0V. The reset voltage can be lowered by increasing the value of the 2K resistor. The circuit operates effectively with capacitors ranging from 4700µF to 1F and is compatible with various motors.

The ALF circuit's limitations in power efficiency when used as a voltage comparator highlight the importance of optimizing the design for low power consumption. The introduction of the dual slope sampling SE circuit addresses these inefficiencies by implementing a sampling mechanism that operates during both the charging and discharging phases of the storage capacitor. This dual sampling approach ensures that the comparator input voltage is monitored continuously, allowing for more precise control over the discharge process and minimizing premature discharges that can occur when the input voltage is not sampled.

In practical applications, the DS SE circuit can significantly enhance the operational efficiency of devices such as the Power Smart Head. By maintaining a low standby current and utilizing solar energy effectively, the circuit can prolong the operational time of the device while ensuring that the storage capacitor remains adequately charged. The design also allows for flexibility in component selection, enabling the use of various capacitor sizes and types, which can be advantageous in different application scenarios.

The implementation of a bicore oscillator further contributes to the efficiency of the DS SE circuit by providing precise control over the sampling period and pulse width. This allows for fine-tuning of the circuit’s response to varying input conditions, ensuring optimal performance across a range of operational scenarios. The use of a transistor front end in the comparator stage enhances the sensitivity and accuracy of the voltage comparisons, which is crucial for applications requiring precise voltage monitoring.

Overall, the advancements in the dual slope sampling SE circuit represent a significant improvement over traditional designs, offering a more efficient and reliable solution for low-power applications that require effective voltage comparison and control.If you had time to experiment with the ALF type SE circuit you may have discovered some of its shortcomings with regard to a Power Smart Head adaptation. The problem is that HCMOS gates are power hungry when used as SE voltage comparators when the analog input voltage is near the CMOS switching threshold.

If an HCMOS gate is used without sampling, the chip supply current can be as high as 70mA with the comparator input voltage near the trigger threshold ( Vcc / 2). Sampling the analog input voltage, which represents the level of Vcc, with narrow pulses can reduce power supply current by the on / off ratio of the sampling pulse width.

With the ALF circuit the worst case average current during a sampling period with a comparator input voltage near the threshold is reduced to less than 100uA although the peak currents will still be in the 50ma range. Once the ALF circuit is triggered, the rest of the circuit which the SE controls is enabled and becomes active.

During this active period, the main storage capacitor is quickly discharged through the load with a duration much shorter than the charging time. This is an important consideration since the same high chip supply current s caused by analog voltages at the comparator input during charging also occur during the discharge period.

For circuits like the Power Smart Head, that have a low power standby mode when locked on to balanced light, the discharge time can take much longer. In the standby mode, the total circuit supply current may be less than 1mA which would conserve the charge on the main capacitor to many tens of minutes if it were not for the inefficient method used to compare the reset voltage level.

During the discharge, the analog comparator input voltage is not sampled and the chip current will rapidly increase and prematurely discharges the storage capacitor. The dual slope sampling SE is the first SE of it`s kind which samples the voltage comparator input voltage during charging AND during discharging.

If the Power Smart Head is in standby, the storage capacitor will likely remain fully charged provided the <1mA supply current is available from the solar cell. The DS SE uses about the same number of components for the SE part as the ALF circuit but the circuit performance is improved several ways.

A bicore circuit was used for the oscilator to set the sample period and pulse width. This grounded bicore can control the pulse duty cycle by switching the reference voltage to the timing resistors from positive to Vcc to change the pulse output from positive to negative pulses. The comparator uses a transistor front end to amplify the 1. 2V reference voltage. The latch and the oscillator outputs connected through 200K resistors with a summed sampling voltage applied to the diode and transistor base emitter junction.

The two resistors form a divide-by-two circuit so the trigger level is approximately 2 x 1. 2V = 2. 4V and a trigger level of 2. 1V that is just 300mV lower. Other resistor ratios should give different trigger and reset voltages. While charging, the sampling circuit analog output voltage that is applied to the left hand comparator inverter input is mostly near 0V but the circuit generates narrow pulses that approach Vcc / 2 when the trigger level is reached. Conversely, while discharging, the sampling circuit output voltage that is applied to the left hand comparator inverter input is mostly near Vcc and now the circuit generates narrow pulses that approach Vcc / 2 when the reset level is reached.

The maximum supply current during charging is <60uA and when triggered the standby current is <100uA. Given the above component values, the trigger level is 2. 5V and the reset voltage is 2. 0V. The reset voltage can be lowered by increasing the value of the 2K resistor. The circuit works well with 4700uF to 1F capacitor s and a variety of motors. 🔗 External reference