Monster Memory

A discussion recently on the mp3projects discussion board about using DRAM memory with small 8-bit processors without DRAM controllers got me to take up an old idea. I thought it should be possible to hook up a DRAM to a small processor (in this case an Atmel 8515) and handle the RAS/CAS sequencing and refresh in software. As DRAM is much cheaper than SRAM, it would be possible to get a large (>500kB) memory at a reasonable price. There would obviously be a speed penalty, but in some cases, this would be of no importance.

The proposed circuit involves interfacing dynamic random-access memory (DRAM) with an Atmel 8515 microcontroller, a common 8-bit processor. The Atmel 8515 features a 16-bit address bus and an 8-bit data bus, which makes it suitable for interfacing with DRAM configurations. The basic concept entails using the microcontroller to manage all necessary control signals, specifically the Row Address Strobe (RAS) and Column Address Strobe (CAS), which are essential for accessing data stored in the DRAM.

The DRAM chip should be selected based on the desired capacity and speed specifications, ensuring compatibility with the microcontroller's operational frequency. A typical configuration could involve using a 512k x 8 DRAM chip, which provides the required memory capacity. The memory chip will be connected to the microcontroller's data bus, with the address lines connected to the microcontroller's output pins.

To implement the RAS/CAS sequencing, the microcontroller will need to generate the appropriate timing signals. This can be achieved by programming the microcontroller to issue RAS and CAS signals in a timed sequence according to the DRAM's specifications. The refresh operation, which is required to maintain data integrity in DRAM, can also be handled by the microcontroller through a software routine that periodically activates the RAS line for each row of memory.

It is important to note that while this approach allows for a significant reduction in memory costs, it does introduce a latency in memory access times compared to SRAM. The access times for DRAM are generally slower, which may affect overall system performance in applications requiring rapid data retrieval. However, for applications where memory cost is a critical factor and speed is less of a concern, this method provides an effective solution.

In summary, the circuit design for interfacing DRAM with an Atmel 8515 microcontroller involves careful consideration of the memory chip selection, timing signal generation, and refresh management, all of which can be accomplished through software control. This configuration allows for the utilization of larger memory capacities at a reduced cost, making it a viable option for specific embedded system applications.A discussion recently on the mp3projects discussion board, about using DRAM memory with small 8-bit processors without DRAM controllers, got me to take up an old idea. I thought it should be possible to hook up a DRAM to a small processor (in this case an Atmel 8515), and handle the RAS/CAS sequencing and refresh in software.

As DRAM is MUCH cheaper than SRAM, it would be possible to get a large (>500kB) memory at a reasonable price. There would obviously be a speed penalty, but in some cases, this would be of no importance. 🔗 External reference