S/R Flip-Flop


Posted on Mar 11, 2013

This circuit combines the characteristics of an asynchronous S/R flip-flop and an edge-triggered JK flip-flop. It changes sta


S/R Flip-Flop
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te on the leading edges of its inputs, and ignores the levels at all other times. In operation, outputs of both D flip-flops are normally high, going low for brief periods after seeing an edge at their respective clock inputs.




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