Posted on Aug 17, 2012

The design incorporates 30-0, 1/4;.. microstrip lines on the input and output. C3, C4, C7, and C8, along with Ll, form a pi network that matches the low-input impedance of the device to 50 0. C5, C6, C9, ClO, and 30-0 transmission line L2 form an output pi network that maximizes power transfer to 50 0. ClO is not always necessary, depending on variations among devices and circuitboard material.

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Bias is provided by Rl, R2, and Dl. Rl can be optimized, if desired, to adjust the collector idling current.

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