Video amplifier provides digital gain control

Gain-change settling time is lower than 30 nsec. The greater-than-100-MHz bandwidth of each stage results in an overall passband for all gain settings of greater than 60 MHz. The five lowpass-bandpass capacitors, C1 through C5, determine the lower end of the passband. In the original application, the frequencies of interest don't extend much below 100 kHz. So, using 0.1-µF capacitors results in a roll-off of approximately 50 kHz. Larger values for these capacitors would reduce this figure. Omitting the capacitors for a dc response is not recommended, however, because the resulting amplification of IC1's input offset would produce an output offset in the order of volts at high gain settings. You can generate the gain-programming word using any TTL-compatible, 8-bit parallel-I/O port, such as a PC's parallel printer port or an EIA-1284-compatible port. The HCT04 CMOS inverter chip in the gain-control pathway blocks any possible noise entry in the gain-control lines. The overall input-referred voltage noise is approximately 2 nV per the square root of hertz, equivalent to the Johnson noise of a 250W resistor. Maximum output level is 15 dBm (3.6V p-p) into 50W and twice that into high-impedance loads. The combination of extreme gain and high-frequency response (gain-bandwidth products approaching 200 GHz) of this circuit mandates careful attention to issues of ground-plane and power-supply-bypass integrity....