40MHz 32 Channel PC-Based Logic Analyser

It is a 32-channel, 40 MHz, fully PC-controlled TTL/CMOS logic analyzer with internal and external triggering, as well as trigger delay capabilities. The internal triggering is completely maskable (High/Low/Don't Care) across all 32 channels. The entire system is designed to fit on a single-sided PCB with minimal wiring. Unfortunately, the PCLA is not available as a complete kit from any suppliers, and pre-programmed PLDs are no longer sold. Only the software remains available. Therefore, those interested in building the device will need to fabricate the PCB and program the PLDs independently. The PLDs were designed using the older Lattice Semiconductor ispLSI starter kit, but newer development tools are accessible from the Lattice website. It is noted that compatibility issues may arise with these newer tools, and no solutions are provided for these problems. There are no plans to upgrade this project to newer devices or software. Internal schematics for the chips can be found on the website, which may assist in programming the newer devices. It is important to understand that the ispLSI PLD chips are blank upon purchase and must be programmed with the provided JED files to function. A new logic analyzer product developed by Peter Baxter is expected to be available around the end of 2003, with delays attributed to business partnership issues rather than engineering challenges. The previous kit version was completely sold out in 1999, and no units or spare parts are currently available. The website contains information about the kit, but it is no longer active. The new product is anticipated to be worth the wait. Additionally, there is a known issue with the timebase generation circuit that causes inaccuracies in the 10 MHz and lower frequency ranges; specifically, the Q1 output of IC4 produces an 8 MHz clock instead of the intended 10 MHz, leading to timebase inaccuracies for all ranges at or below 10 MHz.

The 32-channel, 40 MHz logic analyzer is designed for versatile applications in digital circuit testing and debugging. It supports TTL and CMOS logic levels, making it suitable for a wide range of digital devices. The analyzer’s capability for both internal and external triggering allows users to capture signals based on specific conditions, enhancing its utility in complex debugging scenarios. The maskable internal triggering feature enables users to selectively monitor specific signal levels across all channels, providing flexibility in signal analysis.

The logic analyzer is implemented on a single-sided PCB, which minimizes assembly complexity and enhances reliability by reducing the potential for wiring errors. However, users must be prepared to fabricate the PCB themselves, as complete kits are no longer available. The programming of the PLDs is a crucial step in the assembly process, as these devices are initially blank and require the appropriate JED files to be functional. The availability of internal schematics aids users in understanding the configuration and functionality of the PLDs, facilitating the programming process.

The reported issue with the timebase generation circuit is significant for users relying on accurate frequency measurements. The incorrect output frequency from the Q1 pin of IC4 necessitates a careful examination of the circuit design and may require modifications to ensure proper clock generation. Users may need to implement corrective measures to address the clock frequency discrepancy, particularly if they are working within the 10 MHz range or lower.

In summary, while the 32-channel, 40 MHz logic analyzer presents a valuable tool for digital analysis, potential builders must possess the requisite skills to fabricate the PCB, program the PLDs, and troubleshoot any issues that may arise during the assembly and operation of the device.It is a 32 Channel, 40Mhz, fully PCcontrolled TTL/CMOSlogic analyser with internal/external triggering and trigger delay. Internal triggering is fully maskable (High/Low/Don`t Care) on all 32 channels. The whole things fits on one single sided PCB with virtually no wiring! Unfortunately the PCLA is not available as a complete kit from any of the k it suppliers, and I no longer sell the pre-programmed PLD`s. Only the software is available. So if you want to build it, then I`m afraid you`ll have to make the PCB and program the PLD`s yourself. The PLD`s were designed with the old Lattice Semiconductor ispLSI starter kit, but the newer Lattice development tools are available from the lattice web site.

I have not used this new software, and email reports indicate that the files on this page are not compatible with it. I do not know how to solve this issue, so please don`t ask. I have no plans to upgrade this project to new devices or software. The internal schematics for the chips are available on this page, you can use these to program the newer devices yourself.

NOTE : I get a *lot* of email about the ispLSI PLDchips in this project. For those of you who are unaware of what they are, they are Programmable Logic Devices, and they are BLANK when you buy them, you MUSTprogram them with the JED files from here in order to get them to work. If you don`t even know this much then you really have no need for this project! Peter Baxter has developed a new Logic Anlyser product that should be on the market around the end of 2003.

The delay is due to Business Partner issues, rather than engineering aspects. The earlier kit version completely sold out in 1999. There are no units available and no spare parts. You can look at the website: for info on the kit, but don`t get excited by it. It is closed. The new one will be worth the wait. There is a problem with the timebase generation circuit that causes the 10MHz and lower ranges to be inaccurate. The basic problem is that the Q1 output of IC4 does not produce a 10MHz clock, but 8MHz instead, which causes all the ranges 10MHz and below to have an inaccurate timebase.

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