2 transistor buffer

  
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When designed with general purpose small-signal transistors, the bandwidth is 50MHz to 250MHz so very careful grounding and power supply decoupling is required. Simulation schematic for 2 transistor buffer. *Copyright Poul Petersen 2009 * *Some standard Spice stuff.
2 transistor buffer - schematic

Due to copyright issues models from other sources are not *included here. They can be downloaded from the manufacturers` *web sites. . Lib C:LIBsSpiceetex_dl. lib * *Signal generator VIN 101 0 AC 1 SINE(0 5 1000 0 0 0) * *Power supply Vcc Vcc 0 30 * *Load resistor value. PARAM Rl=10K. STEP PARAM Rl LIST 100 1000 10000 *100R load resistance is included to emphasize the clipping of the *single transistor circuit. Cross over distortion is very high into *100R for the 2 transistor circuit. * *Single transistor buffer. R111 101 11 1 ; Series resistor from generator. C11 11 12 10u R11 Vcc 12 47K R12 12 0 47K Q11 Vcc 12 13 ZTX653 ; from R13 13 0 3K C12 13 14 220u R14 14 0 {Rl} * *2 Transistor buffer with single supply. R121 101 21 1 ; Series resistor from generator. C21 21 22 10u R21 Vcc 22 47K R22 22 0 47K Q21 Vcc 22 24 ZTX653 ; from R23 24 0 5. 9K Q22 0 22 23 ZTX753 ; from R24 Vcc 23 5. 9K C22 23 25 100u C23 24 25 100u R25 25 0 {Rl} * ;. DC TEMP 0 70 10. AC DEC 10 100m 1MEG ;. NOISE V(25) VIN DEC 10 10 100K ;. TRAN 2m. PROBE. END *



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