A practical MS Decoder Circuit

Posted on Feb 4, 2014

The schematic diagram of the MS Decoder may look complicated but is actually quite simple. Both the Mid and Side signals are initially buffered by unity gain inverting buffers formed around IC1b and IC2 b. This is necessary for two reasons, first to ensure enough drive current for the following sections. Second, the final summing sections invert t

A practical MS Decoder Circuit
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he signal, to achieve zero phase shift through the unit, one more stage of phase inversion is required. The Mid signal goes to level control potentiometer R15. It is then fed equally to the left and right summing amplifiers, which are formed around the two sections of IC3. The use of R15 (and R16) is to allow adjustment of the relative levels of the mid/side levels independent of the mic-pre gain setting. This is useful for directly feeding a recording device. The Side signal has a little different path. After initial buffering, it is fed to the right summing amplifier via one section of dual potentiometer R16. It is also fed to a unity gain inverter formed by IC2a and its associated resistors. This inverted signal goes to the other half of the dual ganged potentiometer section. Then it is summed into the left channel via IC3a. One section of IC1 is not used. Both of its inputs are tied to ground to keep any thing strange from happening. OK, so what are R19 and R20 doing That is an interesting question. These are there to load down R16 so that when the levels of the Side signal are adjusted the potentiometer gives the same feel as the Mid level adjustment potentiometer R15. The op-amp summing sections are virtual grounds. This means that signals entering the op-amp see a load equal to the input resistor. All of these are 10K resistors. The Mid potentiometer feeds two of these so it is presented with a 5K load. To make the...

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