CMOS Integrated Switched-Mode Transmitters for Wireless Communication

Measured output power and efficiency of a 6 dBm 130nm CMOS class-D inverter chain, using gate bias variation to create a pulse width modulated inverter output voltage (Cijvat et al. , 2008). (b). Efficiency versus output power of two amplifiers, one with 6dBm and one with 12 dBm output power. The supply voltage was 1. 2 V. The 6 dBm amplifier operated at 1. 5 GHz, the 12 dBm amplifier at 1 GHz.
CMOS Integrated Switched-Mode Transmitters for Wireless Communication - schematic

Figure 5. Simulated PA drain efficiency versus output power, combining EER modulation for high amplitudes and PWM for lower amplitudes. The voltage where EER takes over is varied; one curve shows results for a border value of 0. 6V and the second curve for a border value of 0. 9V. Figure 8. Simulated drain efficiency for a CMOS class-D amplifier in different architectures, such as Envelope Elimination and Restoration (EER), Envelope Tracking (ET), and Pulse Width Modulation by Variable Gate Bias (PWMVGB). Class-A and class-B curves serve only as an illustration. The amplifier operated on a 1. 2V supply and the input signal had a frequency of 2 GHz. (a). The output power (x-axis) represented in dBm, (b). The output power in mW. Power amplifiers (PAs) determine much of the efficiency and linearity of transmitters in wireless communication systems, both on the base station side and in the handset device. With the move to third-generation (3G) communication systems as well as other systems such as Ultra-Wideband (UWB), a higher linearity is required due to envelope variations of the radio frequency (RF) signal. The traditional way of guaranteeing sufficient linearity is backing off the PA; however, this results in a significant drop in efficiency, and thus in reduced battery lifetime for the handheld device and increased cooling requirements for the base station. With the current energy costs, and increased density of base...

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