CPLD Programming


Posted on Feb 5, 2014

This Programming interface circuit sends the programming signals from the USB cable to the FPGA chip directly, through a standardized 10-PIN interface. Technically there are only 4 or 5 signal pins used, excluding GND and unused interface pins from the 10-PIN Ribbon cable that is commonly used by JTAG controllers. Almost all FPGA and


CPLD Programming
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CPLD components have a set of devoted pins on the chip for this JTAG "In-System-Programming" interface. Here below is an older Altera MAX7000S CPLD chip which supports this JTAG interface used for special applications including a feature called "ISP" or In-System-Programming. I have highlighted the JTAG interface pins in Yellow for your convenience. So all that is needed in order to program this chip, is to connect these JTAG pins from the chip to a USB-Blaster circuit. You then also connect all of the chips VCC and GND pins to source power and. The USB-Blaster or "JTAG" programming circuit is also available as an external JTAG controller called the "ALTERA USB-Blaster" as seen in the images below. There was an older version of this JTAG controller called the Altera "BYTE-BLASTER-II" and it connected to your PC`s 25pin Parallel printer port. Having this "USB-BLASTER" JTAG controller gives you the option to program other CPLD`s and FPGA`s that provide the JTAG interface and support the "ISP" (In-Service-Programming) feature. In turn, you can build your own PCB`s and program an Altera CPLD or FPGA device with your own logic design. The chip is programmed the same way you program your Altera development board through Quartus or your logic Synthesis software of choice. Many of the older Altera CPLD chips require a special Master Programming unit, in order to be programmed and do not support the JTAG interface at all. The...




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