CS63 Programming Project

An 8x8-bit memory module was designed using LogicSim, a shareware software program that facilitates the creation of logic diagrams and the simulation of those designs. The memory module incorporates 688 logic gates and features multiple layers of abstraction to maintain organization and clarity. The initial attempt was to implement a 7x8-bit memory module, which required 938 logic gates and proved to be overly complex. A subsequent attempt at a 12x8-bit module resulted in program crashes during simulation, leading to the decision to finalize the design as an 8x8-bit memory module. This design is simpler and more comprehensible compared to the original 7x8-bit module. The 688 logic gates in this module are a significant reduction from the previous design. A flaw in the earlier design caused memory purging when either the RW or CE inputs changed, which has since been addressed. The 8x8-bit memory module features several components: on the left side, there are switches labeled L0-L7 for data input, and A0-A2 for address input. The signals CE, RW, and OE denote chip enable, read/write, and output enable, respectively. The address lines connect to a 3-to-8 decoder that selects the word to be enabled for reading or writing. The output from the decoder is directed to custom-built 4x4-bit memory modules, labeled W0-W3 and W4-W7, which store the respective 8-bit words. The memory outputs are processed through an OR gate to yield the final output sent to the CPU. Simulation of the circuit was conducted on a PowerMac 7100/80, and the circuit diagram presented is a snapshot of that simulation, alongside diagrams of the custom modules.

The 8x8-bit memory module is a crucial component in digital systems, designed to efficiently store and retrieve data. The choice of using 688 logic gates indicates a careful balance between complexity and functionality, allowing for effective data handling without overwhelming the design. The use of abstraction layers simplifies the representation of the circuit, making it easier for users to understand the operation of the memory module.

The input switches (L0-L7) provide a means for users to enter 8-bit data into the memory. The address switches (A0-A2) allow for the selection of one of the eight memory locations for read or write operations. The chip enable (CE) signal activates the memory module, while the read/write (RW) signal determines whether data is being written to or read from the memory. The output enable (OE) signal is essential for controlling when the data output is valid.

The 3-to-8 decoder plays a pivotal role in the design, translating the 3-bit address input into a corresponding output that activates one of the four memory modules at a time. Each memory module is capable of storing four 8-bit words, effectively allowing the entire memory module to manage a total of eight 8-bit words.

The final output from the memory modules is processed through an OR gate, which combines the outputs of the selected memory modules, ensuring that the correct data is sent to the CPU. This design choice is crucial for maintaining data integrity and ensuring that the CPU receives the desired information.

Simulation results on the PowerMac 7100/80 demonstrate the functionality of the design, confirming that the module operates as intended. The inclusion of custom module diagrams further aids in understanding the internal workings of the memory system, providing a comprehensive overview of the design's architecture and operation. The overall design reflects a well-thought-out approach to memory module architecture, balancing complexity and usability for effective data management in electronic systems.I designed a 8x8-bit memory module using LogicSim, a shareware software program that allows people to create logic diagrams and run a simulation using that design. The memory module I created uses 688 logic gates. There are couple layers of abstraction in the design. I did this for two reasons. First, I wanted to keep the diagram as well organized and as understandable as possible. The other reason was LogicSim does not have a big desktop. Abstraction allowed me to put more words into the memory module. Initially I tried implementing a 7x8-bit memory module (see below). However, that used 938 logic gates. It was a monster. Then I tried at 12x8-bit module. When I tried to run a simulation using the circuit, it crashed the program, so I abandoned that idea. So I settled on the 8x8-bit memory module. This diagram of this module is simpler and easier to follow, compared to my original 7x8-bit module. By the way, the goliath fell hard. This memory module contains 688 logic gates, a far cry from 938. The goliath also suffered from a major flaw. A word in memory was purged when either the RW or CE inputs were changed. I believe I fixed that bug. Please look at my design for a 8x8-bit memory module and tell me what you think. I included the circuit diagrams for the custom modules used in the main circuit diagram. Let me try to explain this diagram so it is less confusing. On the left are many switches. The switches labeled L0-L7 are data input switches. The switches labeled A0-A2 are address switches. CE, RW, and OE stand for chip enable, read/write, and output enable, respectively. The address lines feed into a 3-8 decoder, which determine which word is to be enabled for reading or writing.

The output from the decoder feeds into the 4x4-bit memory modules, which are custom-made. The data lines, as well as CE, RW, and OE, also feed into the memory modules. The modules are labled W0-W3 and W4-W7. That means the module W0-W3 are used to store words 0 through 3 and likewise with W4-W8. Two modules are used to store 4 8-bit words. The output from the memory modules are the values for bits 0 to 7. I should note that although the memory modules have their inputs marked as 0 through 3 and their outputs marked as 0 through 3, only one pair of modules actually stores the values for bits 0 through 3. The other pair stores the values for the bits 4 through 8. The output from the memory modules, are paired and the pair is run through an OR gate. The result is the value memory would send to the CPU. I hope that clears up some things. I tried running a simualtion of the circuit on a PowerMac 7100/80. The circuit diagram you see above is a snapshot of a simulation of the circuit. I have also include circuit diagrams of the custom made modules which are also snapshots of simulations.

Enjoy! 🔗 External reference