JTAG from a router


Posted on Feb 6, 2014    10323

It`s a quick hack on veroboard rather than a neat PCB, but here`s the schematic. Three outputs (TMS, TCK, TDI) run to the 74HC04 for buffering. The /RESET output drives a pull-down NPN transistor directly. Note that the 74HC04 is driven from an external Vcc taken from the target circuit; this allows the output voltage to be controlled by the targe


JTAG from a router
Click here to download the full size of the above Circuit.

t. Supplying 5V, for example, will let TMS, TCK, etc. have a full 0-5V swing; however inputs to the wrtag will result in the 74HC04 outputs driving the GPIOs at greater than 3. 3V. To protect against this, two zener diodes clamp the Misc and TDO inputs to 3. 3V. Also, they have a 50ohm resistor in series in case the input GPIOs are configured as outputs before cblsrv can reconfigure them as inputs. Grotty, but it works; it`s not hugely useful and I end up driving the buffer Vcc from the box`s 3. 3V out anyway ” everything I need to JTAG is currently 3. 3V and any lower will require buffering a little more exotic than a 74HC04. Consider using one of TI`s dual-supply level conversion buffers instead. There are two ethernet ports on this version of the AR7. My kernel initialised them in the wrong order, making eth0 the non-functional PHY-less one, which upset OpenWRT a little. There`s a hacky patch below to just disable probing one, so eth0 works. The code to bit-bang the parallel port has been split into a separate class, which drives pins via a new GpioCtrl class. An implementation of this (in GpioCtrl_ar7. cpp) drives the AR7 GPIOs on the pins listed above. Note that GpioCtrl_ar7. cpp is specific to my wiring ” but the pins are #defined so are easy to change. Note also that their sense is inverted because I`m using an inverter to buffer them! The AR7 GPIOs require a read-modify-write to change a pin state, as there`re no...




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