Memory Circuits

This application note describes a method to automatically detect the memory size of a serial EEPROM connected to an I 2 C bus. The topics include: ? Automatic detection of memory size on the I 2 C bus ? Standard I 2 C ? Smart Serial or the I 2 C Dilemma ? Another set of routines for I 2 C ? How to tell the addressing scheme ? How to tell the size ? Putting it all together ? Debugging ? Compatibility ? References

The PIC18C601 and PIC18C801 are the very first members of Microchip?s PIC18 family that are ROMless microcontrollers ? that is, they have no on-chip program memory. Both offer the enhanced PIC18 architecture, along with the ability to use different types and sizes of external program memory to exactly fit any application. In addition to standard 1.5 Kbytes of general purpose RAM, the PIC18C601 can address up to 256 Kbytes of external program memory, while the PIC18C801 can address up to 2 Mbytes of external program memory.

The PIC18FXXXX family offers the largest range of on-chip enhanced FLASH program memory and the richest selection of peripherals in the current line of Microchip microcontrollers. The PIC18F8XXX subset is made up of 80-pin parts that further extend the capabilities by providing access to external memory devices. Through the addition of external memory devices, an 8-bit application has the power to utilize unprecedented amounts of code or data; up to 2 Mbytes for an 8-bit microcontroller!

The PIC17CXXX family of PICmicro ® microcontrollers has an external program memory interface. Since the PIC17CXXX devices implement a 16-bit instruction word, the external memory must be 16-bits wide. The addressing space of these devices is 64K x 16, which requires 16-bits of address as well. Until a few years ago, the designer had to use two 8-bit latches for addressing and two 8-bit wide memories. Now, many manufacturers of logic and memory devices have developed 16-bit wide devices. These new 16-bit wide devices can simplify the layout, reduce part count and cost as shown in Figure 1.

The circuit converts a 32kΧ16 SuperSync FIFO design to bidirectional (half-duplex) using QuickSwitch QS3390 16-to-8 multiplexer/demultiplexer ICs. This implementation has the following advantages over the traditional tristate-multiplex/demultiplex approach:

A pc board bearing the 16-bit ISA data-bus interface in Fig 1 can adapt automatically to either 8- or 16-bit motherboard slots. The interface comprises three bidirectional octal buffers and glue logic. The glue logic controls transfer direction and output enables.

The Intel 82786 graphics controller does not generate a proper data-transfer cycle if your video RAM (VRAM) is organized into two interleaved banks (Fig 1). The circuit in Fig 2 overcomes this device's deficiency.

The circuit in Fig 1 increases the memory of Analog Devices' 2101 family of fixed-point DSP µPs. The simple scheme uses only three external static-memory devices and no glue logic. With the additional memory, the DSP µP will have 16k words of program memory and 15k words of data memory. (The memory totals include 2k words of internal program memory and 1k word of internal data memory.)

The circuit of Figure 1 provides the termination voltage for both 1.8 and 2.5V memory systems and delivers output current as high as 6A. IC1 includes a step-down controller and two linear-regulator controllers and operates with input voltages of 4.5 to 28V.

This technology allows you to use a section of flash memory as if it were EEPROM. Because this µC is a true-flash device, the maximum number of erase/write cycles is typically 100,000 cycles. The flow chart in Figure 1 and the C code in Listing 1 show the adaptation of a textbook LFSR (linear-finite shift register) to the COP8 flash µC.

The circuit shown below uses three PI5C16861 bus switches. IC1 is used to perform level translation on all control and addressing lines while IC2 and IC3 are used to translate 36 bits of data. All three switches are always enabled because they are used strictly as translators. Notice that if live insertion is required, the bus switch can double as bus isolation. In such a situation, enable pins should be held high with a pullup resistor during insertion.

Fig 1b shows a suggested implementation for a 16th-order filter based on this equation. This implementation requires only 512 locations of ROM compared with 21664k for the direct implementation. Fig 1b uses separate ROMs to store each sum and adds the partial sums together at the ROM outputs.

This circuit sequence through a pattern of Christmas lights to turn on and off each string of lights, one at a time. After sequencing through all strings, the circuit turns the last string off, then turns all strings on, and then off, before repeating the pattern. Some simple wiring changes will let you set up other patterns. This circuit provides for five strings of lights, but you can increase or decrease the number, and adjust the timing.

The circuit in Figure 1 shows the basic configuration of a simple and inexpensive arbitrary waveform generator. IC1’s 82C54 produces the timebase for the wave table. This IC can generate a 152-Hz to 5-MHz clock under software control, which translates to a 1.52-Hz to 50-kHz, 100-point continuous wave of any type. The FIFO AM7201A (IC2) holds the wave information. When FIFO HALT is high, IC3A and IC3B control the loading of the wave into the FIFO by first halting the FIFO read clock at IC2’s pin 15 and deactivating the retransmit line at IC2’s pin 23, respectively. When you then provide a low-going pulse to the FIFO RESET input and a negative edge at FIFO WRITE, you can write the wave information to the input of the FIFO.

Many times, choosing a FLASH memory device is driven by which manufacturer has the cheapest offering. Regardless of its use as a stand-alone device or as the program memory of a microcontroller, what is often overlooked are the many key design parameters, or the features that the memory may offer to the application. Endurance, data retention, temperature, operating voltage and frequency, and programming time all play significant roles in the reliability of the device. Selections based on cost alone may be penny-wise but dollarfoolish; the application may be the cheapest on the market but its overall quality can negatively impact the customer?s perception and therefore, their future purchases.

PLDs ranging from complex, cell-based implementations to FPGAs are no longer merely implementing a few TTL chips' worth of glue logic. Instead, as gate densities move toward 100,000 gates per device and beyond, PLDs are becoming subsystems on a chip. Recognizing this trend, PLD vendors are increasingly incorporating the memory capacity that such subsystems demand.

Many designs require FIFO elastic buffers to form a bridge between subsystems with different clock rates and access requirements. However, in some applications, you need FIFO buffers for data conversion. One example is the case in which you need to connect an 8-bit ADC to a 16-bit data-bus microprocessor through a FIFO buffer (Figure 1).

The circuit in Figure 1 is an FPGA-based, synchronous FIFO that uses the same clock for read and write operations. The circuit can generate FIFO-occupancy flags with a minimum of logic. The boxed area in Figure 1 shows a more conventional occupancy meter. The circuit is implemented in a demultiplexer that writes data in the FIFO when the data arrives and reads data according to FIFO occupancy. The circuit uses a Xilinx Spartan (XC4000 equivalent) FPGA. The method uses three main blocks: a 16-bit dual-port RAM macro, read- and write-address counters, and the flag processor.

The PIC17CXXX devices have the capability to interface external FLASH memory into the 64K x 16 program memory space. Coupled with this feature is the ability to read and write to the entire program memory of the device. Using one of the standard serial interfaces on the PICmicro (USART, SPI, I 2 C?), a complete hex file can be downloaded into the external FLASH memory by a bootloader program. The PIC17CXXX family consists of seven devices as shown in Table 1

Many applications require the microcontroller to calculate a checksum on the program memory to determine if the contents have been corrupted. Until now, the only family of PICmicro ® microcontrollers to have the capability to read from program memory are the PIC17CXXX devices. The PIC16F87X devices are the first 14-bit core PICmicro microcontrollers that are able to access program memory in the same fashion as used with data EEPROM memory. These devices are FLASH extensions of the popular PIC16C7X family. Table 1 shows a comparison between the two PICmicro microcontroller families.