Memory Circuits

Some RISC controllers, like the NEC V850 family, use an internal 32-bit architecture with an external 16-bit bus. The architecture also allows interfaces with 8-bit memories. However, with 8-bit memories, accesses to and from odd locations automatically access the higher-order byte. Thus, you would need external transceivers to access both even and odd locations. However, you can "trick" the processor and thereby save the space and cost associated with the external transceivers. Like everything else in life, the method doesn't come free—the price you pay is execution time.

This programmer was designed in view of to be flexible, economical and easy to built, the programmer hardware utilizes the standard TTL series parts and no special components are used. The programmer is interfaced with the PC parallel port and there is no special requirement for the PC parallel port, so the older computers can also be used with this programmer.

You use the fully controlled circuit in Figure 1 to parallel-program two-wire serial EEPROMs via the I2C bus. Gang programmers must address all memory devices during a write operation. To verify the memory contents, however, the system must address only one memory at a time during read operations. Therefore, the system in Figure 1 addresses the memory devices either in parallel or one at a time. Information transfer between devices connected to the I2C bus system requires a SDA (serial-data) and SCL (serial-clock) signals.

The demand for higher memory speeds has resulted in evolution of the established PC100 / PC133 SDRAM to the newer Double Data Rate (DDR) SDRAM which clocks data on both positive and negative transitions of the clock, two data transfers per clock cycle result in a data rate of 266 MHz while the command and address lines only transition on the positive clock edges for a 133 MHz rate, speed grades for DDR allow for both 200 MHz and 266 MHz data transfer rates.

Dynamic memory allocation is a nice functionality that is provided with virtually all PC-based compilers. However, not all microcontroller compilers have such capability, most likely due to the lack of a sophisticated operating system with memory management. Although most applications are static in nature, there are cases where a need for dynamic allocation of memory resources exists. Examples include any number of network protocols that have a dynamically specified nature. This application note presents a simple and efficient method for dynamic memory allocation without the need of an operating system.

PLDs ranging from complex, cell-based implementations to FPGAs are no longer merely implementing a few TTL chips' worth of glue logic. Instead, as gate densities move toward 100,000 gates per device and beyond, PLDs are becoming subsystems on a chip. Recognizing this trend, PLD vendors are increasingly incorporating the memory capacity that such subsystems demand.

The PIC17CXXX family of PICmicro ® microcontrollers has an external program memory interface. Since the PIC17CXXX devices implement a 16-bit instruction word, the external memory must be 16-bits wide. The addressing space of these devices is 64K x 16, which requires 16-bits of address as well. Until a few years ago, the designer had to use two 8-bit latches for addressing and two 8-bit wide memories. Now, many manufacturers of logic and memory devices have developed 16-bit wide devices. These new 16-bit wide devices can simplify the layout, reduce part count and cost as shown in Figure 1.

The PIC18C601 and PIC18C801 are the very first members of Microchip?s PIC18 family that are ROMless microcontrollers ? that is, they have no on-chip program memory. Both offer the enhanced PIC18 architecture, along with the ability to use different types and sizes of external program memory to exactly fit any application. In addition to standard 1.5 Kbytes of general purpose RAM, the PIC18C601 can address up to 256 Kbytes of external program memory, while the PIC18C801 can address up to 2 Mbytes of external program memory.

The circuit in Figure 1 shows the basic configuration of a simple and inexpensive arbitrary waveform generator. IC1’s 82C54 produces the timebase for the wave table. This IC can generate a 152-Hz to 5-MHz clock under software control, which translates to a 1.52-Hz to 50-kHz, 100-point continuous wave of any type. The FIFO AM7201A (IC2) holds the wave information. When FIFO HALT is high, IC3A and IC3B control the loading of the wave into the FIFO by first halting the FIFO read clock at IC2’s pin 15 and deactivating the retransmit line at IC2’s pin 23, respectively. When you then provide a low-going pulse to the FIFO RESET input and a negative edge at FIFO WRITE, you can write the wave information to the input of the FIFO.

Fig 1b shows a suggested implementation for a 16th-order filter based on this equation. This implementation requires only 512 locations of ROM compared with 21664k for the direct implementation. Fig 1b uses separate ROMs to store each sum and adds the partial sums together at the ROM outputs.