Memory Circuits

I had been putting off writing a driver for some 24LC64 and 24LC256 EEPROMS I was thinking about using, when I came across a temperature logger application written by Seal Ellis. The Temperature logger was posted on on www.avrfreaks.net on January 10, 2002, project ID 49. The original application was written for the ATtiny15, whichhas a small hardware stack, so when extracting the I2C code, I massaged it a little bit to make it more compact when running on processors equipped with a RAM stack while making it a little easier to customize for new applications. ..

The four 1K resistors on the output of U6 are too high in value for some parallel ports. Change these to 100ohm. Some LSI based parallel ports use active pull-up resistors and these are lower than the nominal 4K7 which causes a voltage divider effect. A bad design mistake. The eight LED dropper resistors are too low in value and cause pikes on the power rails which can effect the rest of the circuit. Change these resistors to 1K or greater. Another bad design mistake...

Interfacing DRAM M5M44800 Memory with AVR AT90S8515

Is it possible to use DRAM with microcontroller AVR? Yes, it is possible. Jesperh has proved it. He hooked up a DRAM to a small processor (in this case an Microcontroller Atmel 8515), and handle the RAS/CAS sequencing and refresh in software. The type of DRAM is Hitatchi M5M44800, a 512k*8 DRAM!. Bigger than the original memory of microcontroller AT90S8515 that is 512 byte RAM. The project use C to programm it. The chip required small power consumption, only takes about 2-3 mA when just refreshing and with a low access rate. ..

The VPP generator circuits shown here cover a range of 30mA to 240mA with 3.3V or 5V inputs as noted. Table 1 summarizes these circuits for quick reference...

The demand for higher memory speeds has resulted in evolution of the established PC100 / PC133 SDRAM to the newer Double Data Rate (DDR) SDRAM which clocks data on both positive and negative transitions of the clock, two data transfers per clock cycle result in a data rate of 266 MHz while the command and address lines only transition on the positive clock edges for a 133 MHz rate, speed grades for DDR allow for both 200 MHz and 266 MHz data transfer rates...

Some RISC controllers, like the NEC V850 family, use an internal 32-bit architecture with an external 16-bit bus. The architecture also allows interfaces with 8-bit memories. However, with 8-bit memories, accesses to and from odd locations automatically access the higher-order byte. Thus, you would need external transceivers to access both even and odd locations. However, you can "trick" the processor and thereby save the space and cost associated with the external transceivers. Like everything else in life, the method doesn`t come freethe price you pay is execution time...

This application note describes the COP8 In System Programming (ISP) Software. ISP method of programming the flash memory are thoroughly discussed...

This programmer was designed in view of to be flexible, economical and easy to built, the programmer hardware utilizes the standard TTL series parts and no special components are used. The programmer is interfaced with the PC parallel port and there is no special requirement for the PC parallel port, so the older computers can also be used with this programmer...

You use the fully controlled circuit in Figure 1 to parallel-program two-wire serial EEPROMs via the I2C bus. Gang programmers must address all memory devices during a write operation. To verify the memory contents, however, the system must address only one memory at a time during read operations. Therefore, the system in Figure 1 addresses the memory devices either in parallel or one at a time. Information transfer between devices connected to the I2C bus system requires a SDA (serial-data) and SCL (serial-clock) signals...

The circuit in Figure 1 is an FPGA-based, synchronous FIFO that uses the same clock for read and write operations. The circuit can generate FIFO-occupancy flags with a minimum of logic. The boxed area in Figure 1 shows a more conventional occupancy meter. The circuit is implemented in a demultiplexer that writes data in the FIFO when the data arrives and reads data according to FIFO occupancy. The circuit uses a Xilinx Spartan (XC4000 equivalent) FPGA. The method uses three main blocks: a 16-bit dual-port RAM macro, read- and write-address counters, and the flag processor...

Many designs require FIFO elastic buffers to form a bridge between subsystems with different clock rates and access requirements. However, in some applications, you need FIFO buffers for data conversion. One example is the case in which you need to connect an 8-bit ADC to a 16-bit data-bus microprocessor through a FIFO buffer (Figure 1)...

PLDs ranging from complex, cell-based implementations to FPGAs are no longer merely implementing a few TTL chips` worth of glue logic. Instead, as gate densities move toward 100,000 gates per device and beyond, PLDs are becoming subsystems on a chip. Recognizing this trend, PLD vendors are increasingly incorporating the memory capacity that such subsystems demand...

The circuit in Figure 1 shows the basic configuration of a simple and inexpensive arbitrary waveform generator. IC1s 82C54 produces the timebase for the wave table. This IC can generate a 152-Hz to 5-MHz clock under software control, which translates to a 1.52-Hz to 50-kHz, 100-point continuous wave of any type. The FIFO AM7201A (IC2) holds the wave information. When FIFO HALT is high, IC3A and IC3B control the loading of the wave into the FIFO by first halting the FIFO read clock at IC2s pin 15 and deactivating the retransmit line at IC2s pin 23, respectively. When you then provide a low-going pulse to the FIFO RESET input and a negative edge at FIFO WRITE, you can write the wave information to the input of the FIFO...

This circuit sequence through a pattern of Christmas lights to turn on and off each string of lights, one at a time. After sequencing through all strings, the circuit turns the last string off, then turns all strings on, and then off, before repeating the pattern. Some simple wiring changes will let you set up other patterns. This circuit provides for five strings of lights, but you can increase or decrease the number, and adjust the timing...

Fig 1b shows a suggested implementation for a 16th-order filter based on this equation. This implementation requires only 512 locations of ROM compared with 21664k for the direct implementation. Fig 1b uses separate ROMs to store each sum and adds the partial sums together at the ROM outputs...