The monitoring circuit consists of four tri-color LEDs driven by an equal number of op amps configured as gain-of-one inverting amplifiers. Each LED is wired in the circuit so that it glows red when the input to the op amp is high, and green when the input is low. The LED remains off when the input is disconnected from a circuit, when it's at ground potential, and when it's connected to a 3-state output that's in the high-impedance state. Each input has an impedance of.....
You use the fully controlled circuit in Figure 1 to parallel-program two-wire serial EEPROMs via the I2C bus. Gang programmers must address all memory devices during a write operation. To verify the memory contents, however, the system must address only one memory at a time during read operations. Therefore, the system in Figure 1 addresses the memory devices either in parallel or one at a time. Information transfer between devices connected to the I2C bus system requires.....
A pc board bearing the 16-bit ISA data-bus interface in Fig 1 can adapt automatically to either 8- or 16-bit motherboard slots. The interface comprises three bidirectional octal buffers and glue logic. The glue logic controls transfer direction and output enables...
The circuit in Fig 1 increases the memory of Analog Devices` 2101 family of fixed-point DSP µPs. The simple scheme uses only three external static-memory devices and no glue logic. With the additional memory, the DSP µP will have 16k words of program memory and 15k words of data memory. (The memory totals include 2k words of internal program memory and 1k word of internal data memory.)..
This programmer was designed in view of to be flexible, economical and easy to built, the programmer hardware utilizes the standard TTL series parts and no special components are used. The programmer is interfaced with the PC parallel port and there is no special requirement for the PC parallel port, so the older computers can also be used with this programmer...
This circuit sequence through a pattern of Christmas lights to turn on and off each string of lights, one at a time. After sequencing through all strings, the circuit turns the last string off, then turns all strings on, and then off, before repeating the pattern. Some simple wiring changes will let you set up other patterns. This circuit provides for five strings of lights, but you can increase or decrease the number, and adjust the timing...
The circuit of Figure 1 provides the termination voltage for both 1.8 and 2.5V memory systems and delivers output current as high as 6A. IC1 includes a step-down controller and two linear-regulator controllers and operates with input voltages of 4.5 to 28V...
I had been putting off writing a driver for some 24LC64 and 24LC256 EEPROMS I was thinking about using, when I came across a temperature logger application written by Seal Ellis. The Temperature logger was posted on on www.avrfreaks.net on January 10, 2002, project ID 49. The original application was written for the ATtiny15, whichhas a small hardware stack, so when extracting the I2C code, I massaged it a little bit to make it more compact when running on processors.....
The demand for higher memory speeds has resulted in evolution of the established PC100 / PC133 SDRAM to the newer Double Data Rate (DDR) SDRAM which clocks data on both positive and negative transitions of the clock, two data transfers per clock cycle result in a data rate of 266 MHz while the command and address lines only transition on the positive clock edges for a 133 MHz rate, speed grades for DDR allow for both 200 MHz and 266 MHz data transfer rates...
Is it possible to use DRAM with microcontroller AVR? Yes, it is possible. Jesperh has proved it. He hooked up a DRAM to a small processor (in this case an Microcontroller Atmel 8515), and handle the RAS/CAS sequencing and refresh in software. The type of DRAM is Hitatchi M5M44800, a 512k*8 DRAM!. Bigger than the original memory of microcontroller AT90S8515 that is 512 byte RAM. The project use C to programm it. The chip required small power consumption, only takes about.....
Fig 1b shows a suggested implementation for a 16th-order filter based on this equation. This implementation requires only 512 locations of ROM compared with 21664k for the direct implementation. Fig 1b uses separate ROMs to store each sum and adds the partial sums together at the ROM outputs...
This application note describes the COP8 In System Programming (ISP) Software. ISP method of programming the flash memory are thoroughly discussed...
The circuit shown below uses three PI5C16861 bus switches. IC1 is used to perform level translation on all control and addressing lines while IC2 and IC3 are used to translate 36 bits of data. All three switches are always enabled because they are used strictly as translators. Notice that if live insertion is required, the bus switch can double as bus isolation. In such a situation, enable pins should be held high with a pullup resistor during insertion...
Some RISC controllers, like the NEC V850 family, use an internal 32-bit architecture with an external 16-bit bus. The architecture also allows interfaces with 8-bit memories. However, with 8-bit memories, accesses to and from odd locations automatically access the higher-order byte. Thus, you would need external transceivers to access both even and odd locations. However, you can "trick" the processor and thereby save the space and cost associated with the external.....
The circuit converts a 32k½§16 SuperSync FIFO design to bidirectional (half-duplex) using QuickSwitch QS3390 16-to-8 multiplexer/demultiplexer ICs. This implementation has the following advantages over the traditional tristate-multiplex/demultiplex approach:..
The VPP generator circuits shown here cover a range of 30mA to 240mA with 3.3V or 5V inputs as noted. Table 1 summarizes these circuits for quick reference...
The four 1K resistors on the output of U6 are too high in value for some parallel ports. Change these to 100ohm. Some LSI based parallel ports use active pull-up resistors and these are lower than the nominal 4K7 which causes a voltage divider effect. A bad design mistake. The eight LED dropper resistors are too low in value and cause pikes on the power rails which can effect the rest of the circuit. Change these resistors to 1K or greater. Another bad design mistake...
This technology allows you to use a section of flash memory as if it were EEPROM. Because this µC is a true-flash device, the maximum number of erase/write cycles is typically 100,000 cycles. The flow chart in Figure 1 and the C code in Listing 1 show the adaptation of a textbook LFSR (linear-finite shift register) to the COP8 flash µC...
The circuit in Figure 1 shows the basic configuration of a simple and inexpensive arbitrary waveform generator. IC1s 82C54 produces the timebase for the wave table. This IC can generate a 152-Hz to 5-MHz clock under software control, which translates to a 1.52-Hz to 50-kHz, 100-point continuous wave of any type. The FIFO AM7201A (IC2) holds the wave information. When FIFO HALT is high, IC3A and IC3B control the loading of the wave into the FIFO by first halting the FIFO.....
PLDs ranging from complex, cell-based implementations to FPGAs are no longer merely implementing a few TTL chips` worth of glue logic. Instead, as gate densities move toward 100,000 gates per device and beyond, PLDs are becoming subsystems on a chip. Recognizing this trend, PLD vendors are increasingly incorporating the memory capacity that such subsystems demand...
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