ADC interface conditions high-level signals

  
Designers who build equipment for the industrial market share a widespread problem. At one extreme, they must build equipment that supports ±10V bipolar voltages, often riding on a high common-mode level, a requirement enforced by 30 years of legacy industrial equipment. At the other extreme, the analog signal needs conditioning to match the full-scale range of a low-voltage, single-supply ADC.
ADC interface conditions high-level signals - schematic

The difference amplifiers reject the common-mode voltage on inputs VA and VB. The reference voltage, VR, which the AD780 develops and the ADC and the amplifier share, sets the output common-mode voltage. A single capacitor, C, placed arcros the CFILT pins, lowpass-filters the difference signal, V1–V2. The –3-dB pole frequency is: fP=1/(40,000×π×C). A2 amplifies the difference signal by 1.5. Thus, the total gain of this circuit is 3/10. Figure 2 shows a 10V input signal (top), the signals at the output of each AD628 (middle), and the differential output (bottom). The benefits of this configuration go beyond simply interfacing with the ADC. The circuit improves specifications such as common-mode-rejection ratio, offset voltage, drift, and noise by a factor of because the errors of each AD628 are not correlated. The output demonstrates 85-dB SNR (Figure 3). The two AD628s interface with an AD7450 12-bit, differential-input ADC. The AD7450 easily rejects residual common-mode signals at the output of the difference amplifiers. Figure 4 shows the common-mode error at the output of the AD628. The topmost waveform is a 10V, common-mode input signal. The middle waveform, measuring 150 µV, is the common-mode error measured, differentially, from the output of the two AD628s. The bottom waveform, measuring 80 µV, is the resultant common-mode error.




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