1Ghz Divide-By-N Counter

  
Counter speeds for CMOS- and TTL-programmable counters are limited to under 100 MHz. ECL-type devices can approach
1Ghz Divide-By-N Counter - schematic

a few hundred MHz, but with significant current requirements. However, coupling the dual-modulus-prescaling technique with the available phase-locked-loop synthesizer chips that control the prescaler circumvents these frequency and power-drain constraints. With this approach, designers can also choose various counter-programming schemes (serial, parallel, or data bus), in addition to achieving higher frequency capabilities. Low-power drain (less than 75 mW) and low-cost devices can also be selected. Moreover, only two ICs are necessary to achieve divide values above 131000. Maximum input frequency and dividing range for the counter are controlled by choosing an appropriate 8-pin dual-modulus prescaler. The counter"s output appears at synthesizer pin Fy (see the figure). The total input-to-output divide value is governed by the equation: Ntotal = NxP+A and A represent the value programmed through the serial port into the divide-by-jV and divide-by-A counters. is the lower dual-modulus value that is established by the synthesizer"s modulus-control signal. Typically, A varies from zero to P-l to achieve steps within the system"s divide range. must be equal to or greater than A. N>A then sets a lower limit on NT0tal> which is dictated by Amax = P- 1.




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