Switched-capacitor-adc

  
The CMOS comparator in the successive-approximation system determines each bit by examining tbe charge on a series of binary-weighted capacitors. In tbe first phase of tbe conversion process, the analog input is sampled by closing switch SC and all ST switches, and by simultaneously charging all tbe capacitors to tbe input voltage. In tbe next phase of tbe conversion process, all STand SC switches are opened and the comparator begins identifying bits by identifying the charge on each capacitor relative to the reference voltage.
Switched-capacitor-adc - schematic

In tbe switching sequence, all 8 capacitors are examined separately until all 8 bits are identified, and tben tbe charge-convert sequence is repeated. In tbe first step of tbe conversion phase, tbe comparator looks at tbe first capacitor (binary weight = 128). One pole of tbe capacitor is switched to the reference voltage, and tbe equivalent poles of all the otber capacitors on the ladder are switched to ground. If the voltage at the summing node is greater tban the trip point of the comparator-approximately 1/2 the reference voltage, a bit is placed in tbe output register, and tbe 128-weight capacitor is switched to ground. If tbe voltage at tbe sununing node is less than tbe trip point of the comparator, this 128-weight capacitor remains connected to tbe reference input through tbe remainder of the capacitor-sampling (bit-counting) process. The process is repeated for tbe 64-weight capacitor, tbe 32-weight capacitor, and so forth down tbe line, until all bits are tested. With each step of the capacitor-sampling process, the initial charge is redistributed among the capacitors. The conversion process is successive-approximation, but relies on charge shifting rather tban a successive-approximation register-and referenced/a-to count and weigh the bits from MSB to LSB.




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