Data Acquisition System I

  
The HI-506 multiplexer is used as an analog input selector, controlled by a binary counter to address the appropr
Data Acquisition System I - schematic

iate channel. The HA-5330 is a high-speed sample and hold. The sample/hold con- trol is tied to the status (STS) output of the HI-774A; whenever a conversion is in process, the S/H is in the hold mode. A conversion is initiated when the clock input becomes low; when the clock becomes high, the mux address changes. The mux will be acquiring the next channel while the ADC is converting the present input, held by the S/H. The clock low time should be between 225 ns and 6.5 jus, with the period greater than 8.5 $. With this timing, T/C will be high at the end of a conversion, so the output data will be valid - 100 ns before STS goes low. This allows STS to clock the data into the storage register. The register address will be offset by one; if this is a problem, a 4-bit latch can be added to the input of the storage register. With a 100-kHz clock rate, each channel will be read every 160us.




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